Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (27 commits) x86: Clean up apic.c and apic.h x86: Remove superflous goal definition of tsc_sync x86: dt: Correct local apic documentation in device tree bindings x86: dt: Cleanup local apic setup x86: dt: Fix OLPC=y/INTEL_CE=n build rtc: cmos: Add OF bindings x86: ce4100: Use OF to setup devices x86: ioapic: Add OF bindings for IO_APIC x86: dtb: Add generic bus probe x86: dtb: Add support for PCI devices backed by dtb nodes x86: dtb: Add device tree support for HPET x86: dtb: Add early parsing of IO_APIC x86: dtb: Add irq domain abstraction x86: dtb: Add a device tree for CE4100 x86: Add device tree support x86: e820: Remove conditional early mapping in parse_e820_ext x86: OLPC: Make OLPC=n build again x86: OLPC: Remove extra OLPC_OPENFIRMWARE_DT indirection x86: OLPC: Cleanup config maze completely x86: OLPC: Hide OLPC_OPENFIRMWARE config switch ... Fix up conflicts in arch/x86/platform/ce4100/ce4100.c
This commit is contained in:
Linus Torvalds
@@ -16,21 +16,19 @@
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#include <linux/serial_8250.h>
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#include <asm/ce4100.h>
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#include <asm/prom.h>
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#include <asm/setup.h>
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#include <asm/i8259.h>
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#include <asm/io.h>
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#include <asm/io_apic.h>
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static int ce4100_i8042_detect(void)
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{
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return 0;
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}
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static void __init sdv_find_smp_config(void)
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{
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}
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#ifdef CONFIG_SERIAL_8250
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static unsigned int mem_serial_in(struct uart_port *p, int offset)
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{
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offset = offset << p->regshift;
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@@ -119,6 +117,15 @@ static void __init sdv_arch_setup(void)
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sdv_serial_fixup();
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}
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#ifdef CONFIG_X86_IO_APIC
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static void __cpuinit sdv_pci_init(void)
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{
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x86_of_pci_init();
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/* We can't set this earlier, because we need to calibrate the timer */
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legacy_pic = &null_legacy_pic;
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}
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#endif
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/*
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* CE4100 specific x86_init function overrides and early setup
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* calls.
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@@ -129,6 +136,11 @@ void __init x86_ce4100_early_setup(void)
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x86_platform.i8042_detect = ce4100_i8042_detect;
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x86_init.resources.probe_roms = x86_init_noop;
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x86_init.mpparse.get_smp_config = x86_init_uint_noop;
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x86_init.mpparse.find_smp_config = sdv_find_smp_config;
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x86_init.mpparse.find_smp_config = x86_init_noop;
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x86_init.pci.init = ce4100_pci_init;
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#ifdef CONFIG_X86_IO_APIC
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x86_init.pci.init_irq = sdv_pci_init;
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x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
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#endif
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}
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428
arch/x86/platform/ce4100/falconfalls.dts
Normal file
428
arch/x86/platform/ce4100/falconfalls.dts
Normal file
@@ -0,0 +1,428 @@
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/*
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* CE4100 on Falcon Falls
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*
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* (c) Copyright 2010 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2 of the License.
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*/
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/dts-v1/;
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/ {
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model = "intel,falconfalls";
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compatible = "intel,falconfalls";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,ce4100";
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reg = <0>;
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lapic = <&lapic0>;
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};
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};
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soc@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "intel,ce4100-cp";
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ranges;
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ioapic1: interrupt-controller@fec00000 {
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#interrupt-cells = <2>;
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compatible = "intel,ce4100-ioapic";
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interrupt-controller;
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reg = <0xfec00000 0x1000>;
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};
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timer@fed00000 {
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compatible = "intel,ce4100-hpet";
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reg = <0xfed00000 0x200>;
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};
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lapic0: interrupt-controller@fee00000 {
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compatible = "intel,ce4100-lapic";
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reg = <0xfee00000 0x1000>;
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};
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pci@3fc {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,ce4100-pci", "pci";
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device_type = "pci";
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bus-range = <0 0>;
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ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
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0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
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0x0000000 0 0x0 0x0 0 0x100>;
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/* Secondary IO-APIC */
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ioapic2: interrupt-controller@0,1 {
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#interrupt-cells = <2>;
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compatible = "intel,ce4100-ioapic";
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interrupt-controller;
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reg = <0x100 0x0 0x0 0x0 0x0>;
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assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
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};
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pci@1,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,ce4100-pci", "pci";
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device_type = "pci";
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bus-range = <1 1>;
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ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
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interrupt-parent = <&ioapic2>;
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display@2,0 {
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compatible = "pci8086,2e5b.2",
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"pci8086,2e5b",
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"pciclass038000",
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"pciclass0380";
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reg = <0x11000 0x0 0x0 0x0 0x0>;
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interrupts = <0 1>;
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};
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multimedia@3,0 {
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compatible = "pci8086,2e5c.2",
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"pci8086,2e5c",
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"pciclass048000",
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"pciclass0480";
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reg = <0x11800 0x0 0x0 0x0 0x0>;
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interrupts = <2 1>;
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};
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multimedia@4,0 {
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compatible = "pci8086,2e5d.2",
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"pci8086,2e5d",
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"pciclass048000",
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"pciclass0480";
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reg = <0x12000 0x0 0x0 0x0 0x0>;
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interrupts = <4 1>;
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};
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multimedia@4,1 {
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compatible = "pci8086,2e5e.2",
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"pci8086,2e5e",
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"pciclass048000",
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"pciclass0480";
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reg = <0x12100 0x0 0x0 0x0 0x0>;
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interrupts = <5 1>;
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};
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sound@6,0 {
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compatible = "pci8086,2e5f.2",
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"pci8086,2e5f",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13000 0x0 0x0 0x0 0x0>;
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interrupts = <6 1>;
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};
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sound@6,1 {
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compatible = "pci8086,2e5f.2",
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"pci8086,2e5f",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13100 0x0 0x0 0x0 0x0>;
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interrupts = <7 1>;
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};
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sound@6,2 {
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compatible = "pci8086,2e60.2",
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"pci8086,2e60",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13200 0x0 0x0 0x0 0x0>;
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interrupts = <8 1>;
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};
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display@8,0 {
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compatible = "pci8086,2e61.2",
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"pci8086,2e61",
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"pciclass038000",
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"pciclass0380";
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reg = <0x14000 0x0 0x0 0x0 0x0>;
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interrupts = <9 1>;
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};
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display@8,1 {
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compatible = "pci8086,2e62.2",
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"pci8086,2e62",
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"pciclass038000",
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"pciclass0380";
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reg = <0x14100 0x0 0x0 0x0 0x0>;
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interrupts = <10 1>;
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};
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multimedia@8,2 {
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compatible = "pci8086,2e63.2",
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"pci8086,2e63",
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"pciclass048000",
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"pciclass0480";
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reg = <0x14200 0x0 0x0 0x0 0x0>;
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interrupts = <11 1>;
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};
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entertainment-encryption@9,0 {
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compatible = "pci8086,2e64.2",
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"pci8086,2e64",
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"pciclass101000",
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"pciclass1010";
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reg = <0x14800 0x0 0x0 0x0 0x0>;
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interrupts = <12 1>;
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};
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localbus@a,0 {
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compatible = "pci8086,2e65.2",
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"pci8086,2e65",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x15000 0x0 0x0 0x0 0x0>;
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};
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serial@b,0 {
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compatible = "pci8086,2e66.2",
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"pci8086,2e66",
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"pciclass070003",
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"pciclass0700";
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reg = <0x15800 0x0 0x0 0x0 0x0>;
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interrupts = <14 1>;
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};
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gpio@b,1 {
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compatible = "pci8086,2e67.2",
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"pci8086,2e67",
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"pciclassff0000",
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"pciclassff00";
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#gpio-cells = <2>;
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reg = <0x15900 0x0 0x0 0x0 0x0>;
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interrupts = <15 1>;
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gpio-controller;
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};
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i2c-controller@b,2 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "pci8086,2e68.2",
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"pci8086,2e68",
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"pciclass,ff0000",
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"pciclass,ff00";
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|
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reg = <0x15a00 0x0 0x0 0x0 0x0>;
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interrupts = <16 1>;
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ranges = <0 0 0x02000000 0 0xdffe0500 0x100
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1 0 0x02000000 0 0xdffe0600 0x100
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2 0 0x02000000 0 0xdffe0700 0x100>;
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|
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ce4100-i2c-controller";
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reg = <0 0 0x100>;
|
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};
|
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
|
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compatible = "intel,ce4100-i2c-controller";
|
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reg = <1 0 0x100>;
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|
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gpio@26 {
|
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#gpio-cells = <2>;
|
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compatible = "ti,pcf8575";
|
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reg = <0x26>;
|
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gpio-controller;
|
||||
};
|
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};
|
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|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
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compatible = "intel,ce4100-i2c-controller";
|
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reg = <2 0 0x100>;
|
||||
|
||||
gpio@26 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "ti,pcf8575";
|
||||
reg = <0x26>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
smard-card@b,3 {
|
||||
compatible = "pci8086,2e69.2",
|
||||
"pci8086,2e69",
|
||||
"pciclass070500",
|
||||
"pciclass0705";
|
||||
|
||||
reg = <0x15b00 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <15 1>;
|
||||
};
|
||||
|
||||
spi-controller@b,4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible =
|
||||
"pci8086,2e6a.2",
|
||||
"pci8086,2e6a",
|
||||
"pciclass,ff0000",
|
||||
"pciclass,ff00";
|
||||
|
||||
reg = <0x15c00 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <15 1>;
|
||||
|
||||
dac@0 {
|
||||
compatible = "ti,pcm1755";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <115200>;
|
||||
};
|
||||
|
||||
dac@1 {
|
||||
compatible = "ti,pcm1609a";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <115200>;
|
||||
};
|
||||
|
||||
eeprom@2 {
|
||||
compatible = "atmel,at93c46";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <115200>;
|
||||
};
|
||||
};
|
||||
|
||||
multimedia@b,7 {
|
||||
compatible = "pci8086,2e6d.2",
|
||||
"pci8086,2e6d",
|
||||
"pciclassff0000",
|
||||
"pciclassff00";
|
||||
|
||||
reg = <0x15f00 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
|
||||
ethernet@c,0 {
|
||||
compatible = "pci8086,2e6e.2",
|
||||
"pci8086,2e6e",
|
||||
"pciclass020000",
|
||||
"pciclass0200";
|
||||
|
||||
reg = <0x16000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <21 1>;
|
||||
};
|
||||
|
||||
clock@c,1 {
|
||||
compatible = "pci8086,2e6f.2",
|
||||
"pci8086,2e6f",
|
||||
"pciclassff0000",
|
||||
"pciclassff00";
|
||||
|
||||
reg = <0x16100 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <3 1>;
|
||||
};
|
||||
|
||||
usb@d,0 {
|
||||
compatible = "pci8086,2e70.2",
|
||||
"pci8086,2e70",
|
||||
"pciclass0c0320",
|
||||
"pciclass0c03";
|
||||
|
||||
reg = <0x16800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <22 3>;
|
||||
};
|
||||
|
||||
usb@d,1 {
|
||||
compatible = "pci8086,2e70.2",
|
||||
"pci8086,2e70",
|
||||
"pciclass0c0320",
|
||||
"pciclass0c03";
|
||||
|
||||
reg = <0x16900 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <22 3>;
|
||||
};
|
||||
|
||||
sata@e,0 {
|
||||
compatible = "pci8086,2e71.0",
|
||||
"pci8086,2e71",
|
||||
"pciclass010601",
|
||||
"pciclass0106";
|
||||
|
||||
reg = <0x17000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <23 3>;
|
||||
};
|
||||
|
||||
flash@f,0 {
|
||||
compatible = "pci8086,701.1",
|
||||
"pci8086,701",
|
||||
"pciclass050100",
|
||||
"pciclass0501";
|
||||
|
||||
reg = <0x17800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <13 1>;
|
||||
};
|
||||
|
||||
entertainment-encryption@10,0 {
|
||||
compatible = "pci8086,702.1",
|
||||
"pci8086,702",
|
||||
"pciclass101000",
|
||||
"pciclass1010";
|
||||
|
||||
reg = <0x18000 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
|
||||
co-processor@11,0 {
|
||||
compatible = "pci8086,703.1",
|
||||
"pci8086,703",
|
||||
"pciclass0b4000",
|
||||
"pciclass0b40";
|
||||
|
||||
reg = <0x18800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <1 1>;
|
||||
};
|
||||
|
||||
multimedia@12,0 {
|
||||
compatible = "pci8086,704.0",
|
||||
"pci8086,704",
|
||||
"pciclass048000",
|
||||
"pciclass0480";
|
||||
|
||||
reg = <0x19000 0x0 0x0 0x0 0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
isa@1f,0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "isa";
|
||||
ranges = <1 0 0 0 0 0x100>;
|
||||
|
||||
rtc@70 {
|
||||
compatible = "intel,ce4100-rtc", "motorola,mc146818";
|
||||
interrupts = <8 3>;
|
||||
interrupt-parent = <&ioapic1>;
|
||||
ctrl-reg = <2>;
|
||||
freq-reg = <0x26>;
|
||||
reg = <1 0x70 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -31,6 +31,7 @@
|
||||
#include <asm/apic.h>
|
||||
#include <asm/io_apic.h>
|
||||
#include <asm/mrst.h>
|
||||
#include <asm/mrst-vrtc.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/i8259.h>
|
||||
#include <asm/intel_scu_ipc.h>
|
||||
@@ -268,6 +269,7 @@ void __init x86_mrst_early_setup(void)
|
||||
|
||||
x86_platform.calibrate_tsc = mrst_calibrate_tsc;
|
||||
x86_platform.i8042_detect = mrst_i8042_detect;
|
||||
x86_init.timers.wallclock_init = mrst_rtc_init;
|
||||
x86_init.pci.init = pci_mrst_init;
|
||||
x86_init.pci.fixup_irqs = x86_init_noop;
|
||||
|
||||
|
||||
@@ -100,22 +100,14 @@ int vrtc_set_mmss(unsigned long nowtime)
|
||||
|
||||
void __init mrst_rtc_init(void)
|
||||
{
|
||||
unsigned long rtc_paddr;
|
||||
void __iomem *virt_base;
|
||||
unsigned long vrtc_paddr = sfi_mrtc_array[0].phys_addr;
|
||||
|
||||
sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
|
||||
if (!sfi_mrtc_num)
|
||||
if (!sfi_mrtc_num || !vrtc_paddr)
|
||||
return;
|
||||
|
||||
rtc_paddr = sfi_mrtc_array[0].phys_addr;
|
||||
|
||||
/* vRTC's register address may not be page aligned */
|
||||
set_fixmap_nocache(FIX_LNW_VRTC, rtc_paddr);
|
||||
|
||||
virt_base = (void __iomem *)__fix_to_virt(FIX_LNW_VRTC);
|
||||
virt_base += rtc_paddr & ~PAGE_MASK;
|
||||
vrtc_virt_base = virt_base;
|
||||
|
||||
vrtc_virt_base = (void __iomem *)set_fixmap_offset_nocache(FIX_LNW_VRTC,
|
||||
vrtc_paddr);
|
||||
x86_platform.get_wallclock = vrtc_get_time;
|
||||
x86_platform.set_wallclock = vrtc_set_mmss;
|
||||
}
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
obj-$(CONFIG_OLPC) += olpc.o
|
||||
obj-$(CONFIG_OLPC_XO1) += olpc-xo1.o
|
||||
obj-$(CONFIG_OLPC_OPENFIRMWARE) += olpc_ofw.o
|
||||
obj-$(CONFIG_OLPC_OPENFIRMWARE_DT) += olpc_dt.o
|
||||
obj-$(CONFIG_OLPC) += olpc_ofw.o
|
||||
obj-$(CONFIG_OF_PROMTREE) += olpc_dt.o
|
||||
|
||||
Reference in New Issue
Block a user