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drm/radeon/kms/r6xx+: use new style fencing (v3)

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On r6xx+ a newer fence mechanism was implemented to replace
the old wait_until plus scratch regs setup.  A single EOP event
will flush the destination caches, write a fence value, and generate
an interrupt.  This is the recommended fence mechanism on r6xx+ asics.

This requires my previous writeback patch.

v2: fix typo that enabled event fence checking on all asics
rather than just r6xx+.

v3: properly enable EOP interrupts
Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=29972

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
2010-09-04 05:04:34 -04:00
committed by Dave Airlie
parent 724c80e1d6
commit d0f8a854c3
6 changed files with 64 additions and 17 deletions
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8
drivers/gpu/drm/radeon/radeon_device.c
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@@ -208,6 +208,8 @@ int radeon_wb_init(struct radeon_device *rdev)
return r;
}
/* disable event_write fences */
rdev->wb.use_event = false;
/* disabled via module param */
if (radeon_no_wb == 1)
rdev->wb.enabled = false;
@@ -215,8 +217,12 @@ int radeon_wb_init(struct radeon_device *rdev)
/* often unreliable on AGP */
if (rdev->flags & RADEON_IS_AGP) {
rdev->wb.enabled = false;
} else
} else {
rdev->wb.enabled = true;
/* event_write fences are only available on r600+ */
if (rdev->family >= CHIP_R600)
rdev->wb.use_event = true;
}
}
dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");