ath9k: Configure pll control for AR9485
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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John W. Linville

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d09b17f73f
@@ -1114,6 +1114,8 @@ enum {
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#define AR_RTC_PLL_CONTROL \
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((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
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#define AR_RTC_PLL_CONTROL2 0x703c
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#define AR_RTC_PLL_DIV 0x0000001f
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#define AR_RTC_PLL_DIV_S 0
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#define AR_RTC_PLL_DIV2 0x00000020
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