iommu: io-pgtable: Add ARM Mali midgard MMU page table format

ARM Mali midgard GPU is similar to standard 64-bit stage 1 page tables, but
have a few differences. Add a new format type to represent the format. The
input address size is 48-bits and the output address size is 40-bits (and
possibly less?). Note that the later bifrost GPUs follow the standard
64-bit stage 1 format.

The differences in the format compared to 64-bit stage 1 format are:

The 3rd level page entry bits are 0x1 instead of 0x3 for page entries.

The access flags are not read-only and unprivileged, but read and write.
This is similar to stage 2 entries, but the memory attributes field matches
stage 1 being an index.

The nG bit is not set by the vendor driver. This one didn't seem to matter,
but we'll keep it aligned to the vendor driver.

Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: iommu@lists.linux-foundation.org
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190409205427.6943-2-robh@kernel.org
This commit is contained in:
Rob Herring
2019-02-21 14:23:25 -06:00
parent 0eb2766dd6
commit d08d42de64
3 changed files with 77 additions and 22 deletions

View File

@@ -12,6 +12,7 @@ enum io_pgtable_fmt {
ARM_64_LPAE_S1,
ARM_64_LPAE_S2,
ARM_V7S,
ARM_MALI_LPAE,
IO_PGTABLE_NUM_FMTS,
};
@@ -108,6 +109,11 @@ struct io_pgtable_cfg {
u32 nmrr;
u32 prrr;
} arm_v7s_cfg;
struct {
u64 transtab;
u64 memattr;
} arm_mali_lpae_cfg;
};
};
@@ -209,5 +215,6 @@ extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns;
#endif /* __IO_PGTABLE_H */