Merge branch 'omap-serial' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM OMAP serial updates from Russell King: "This series is a major reworking of the OMAP serial driver code fixing various bugs in the hardware-assisted flow control, extending up into serial_core for a couple of issues. These fixes have been done as a set of progressive changes and transformations in the hope that no new bugs will be introduced by this series. The problems are many-fold, from the driver not being informed about updated settings, to the driver not knowing what the intentions of the upper layers are. The first four patches tackle the serial_core layer, allowing it to provide the necessary information to drivers, and the remaining patches allow the OMAP serial driver to take advantage of this. This brings hardware assisted RTS/CTS and XON/OFF flow control into a useful state. These patches have been in linux-next for most of the last cycle; indeed they predate the previous merge window. They've also been posted to the OMAP people." * 'omap-serial' of git://git.linaro.org/people/rmk/linux-arm: (21 commits) SERIAL: omap: fix hardware assisted flow control SERIAL: omap: simplify (2) SERIAL: omap: move xon/xoff setting earlier SERIAL: omap: always set TCR SERIAL: omap: simplify SERIAL: omap: don't read back LCR/MCR/EFR SERIAL: omap: serial_omap_configure_xonxoff() contents into set_termios SERIAL: omap: configure xon/xoff before setting modem control lines SERIAL: omap: remove OMAP_UART_SYSC_RESET and OMAP_UART_FIFO_CLR SERIAL: omap: move driver private definitions and structures to driver SERIAL: omap: remove 'irq_pending' bitfield SERIAL: omap: fix MCR TCRTLR bit handling SERIAL: omap: fix set_mctrl() breakage SERIAL: omap: no need to re-read EFR SERIAL: omap: remove setting of EFR SCD bit SERIAL: omap: allow hardware assisted IXANY mode to be disabled SERIAL: omap: allow hardware assisted rts/cts modes to be disabled SERIAL: core: add throttle/unthrottle callbacks for hardware assisted flow control SERIAL: core: add hardware assisted h/w flow control support SERIAL: core: add hardware assisted s/w flow control support ... Conflicts: drivers/tty/serial/omap-serial.c
This commit is contained in:
@@ -44,6 +44,8 @@
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#include <plat/omap-serial.h>
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#define OMAP_MAX_HSUART_PORTS 6
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#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
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#define OMAP_UART_REV_42 0x0402
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@@ -51,10 +53,14 @@
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#define OMAP_UART_REV_52 0x0502
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#define OMAP_UART_REV_63 0x0603
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#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
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#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
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#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
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/* SCR register bitmasks */
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#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
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#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
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/* FCR register bitmasks */
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#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
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@@ -71,6 +77,52 @@
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#define OMAP_UART_MVR_MAJ_SHIFT 8
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#define OMAP_UART_MVR_MIN_MASK 0x3f
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#define OMAP_UART_DMA_CH_FREE -1
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#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
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#define OMAP_MODE13X_SPEED 230400
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/* WER = 0x7F
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* Enable module level wakeup in WER reg
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*/
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#define OMAP_UART_WER_MOD_WKUP 0X7F
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/* Enable XON/XOFF flow control on output */
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#define OMAP_UART_SW_TX 0x08
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/* Enable XON/XOFF flow control on input */
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#define OMAP_UART_SW_RX 0x02
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#define OMAP_UART_SW_CLR 0xF0
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#define OMAP_UART_TCR_TRIG 0x0F
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struct uart_omap_dma {
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u8 uart_dma_tx;
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u8 uart_dma_rx;
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int rx_dma_channel;
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int tx_dma_channel;
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dma_addr_t rx_buf_dma_phys;
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dma_addr_t tx_buf_dma_phys;
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unsigned int uart_base;
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/*
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* Buffer for rx dma.It is not required for tx because the buffer
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* comes from port structure.
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*/
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unsigned char *rx_buf;
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unsigned int prev_rx_dma_pos;
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int tx_buf_size;
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int tx_dma_used;
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int rx_dma_used;
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spinlock_t tx_lock;
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spinlock_t rx_lock;
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/* timer to poll activity on rx dma */
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struct timer_list rx_timer;
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unsigned int rx_buf_size;
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unsigned int rx_poll_rate;
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unsigned int rx_timeout;
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};
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struct uart_omap_port {
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struct uart_port port;
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struct uart_omap_dma uart_dma;
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@@ -99,7 +151,6 @@ struct uart_omap_port {
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int context_loss_cnt;
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u32 errata;
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u8 wakeups_enabled;
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unsigned int irq_pending:1;
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int DTR_gpio;
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int DTR_inverted;
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@@ -303,6 +354,34 @@ static void serial_omap_start_tx(struct uart_port *port)
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pm_runtime_put_autosuspend(up->dev);
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}
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static void serial_omap_throttle(struct uart_port *port)
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{
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struct uart_omap_port *up = to_uart_omap_port(port);
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unsigned long flags;
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pm_runtime_get_sync(up->dev);
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spin_lock_irqsave(&up->port.lock, flags);
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up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
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serial_out(up, UART_IER, up->ier);
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spin_unlock_irqrestore(&up->port.lock, flags);
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
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}
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static void serial_omap_unthrottle(struct uart_port *port)
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{
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struct uart_omap_port *up = to_uart_omap_port(port);
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unsigned long flags;
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pm_runtime_get_sync(up->dev);
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spin_lock_irqsave(&up->port.lock, flags);
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up->ier |= UART_IER_RLSI | UART_IER_RDI;
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serial_out(up, UART_IER, up->ier);
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spin_unlock_irqrestore(&up->port.lock, flags);
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
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}
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static unsigned int check_modem_status(struct uart_omap_port *up)
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{
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unsigned int status;
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@@ -504,7 +583,7 @@ static unsigned int serial_omap_get_mctrl(struct uart_port *port)
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static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct uart_omap_port *up = to_uart_omap_port(port);
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unsigned char mcr = 0;
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unsigned char mcr = 0, old_mcr;
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dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
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if (mctrl & TIOCM_RTS)
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@@ -519,8 +598,10 @@ static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
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mcr |= UART_MCR_LOOP;
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pm_runtime_get_sync(up->dev);
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up->mcr = serial_in(up, UART_MCR);
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up->mcr |= mcr;
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old_mcr = serial_in(up, UART_MCR);
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old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
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UART_MCR_DTR | UART_MCR_RTS);
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up->mcr = old_mcr | mcr;
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serial_out(up, UART_MCR, up->mcr);
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
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@@ -654,61 +735,6 @@ static void serial_omap_shutdown(struct uart_port *port)
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free_irq(up->port.irq, up);
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}
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static inline void
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serial_omap_configure_xonxoff
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(struct uart_omap_port *up, struct ktermios *termios)
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{
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up->lcr = serial_in(up, UART_LCR);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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up->efr = serial_in(up, UART_EFR);
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serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
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serial_out(up, UART_XON1, termios->c_cc[VSTART]);
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serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
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/* clear SW control mode bits */
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up->efr &= OMAP_UART_SW_CLR;
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/*
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* IXON Flag:
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* Enable XON/XOFF flow control on output.
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* Transmit XON1, XOFF1
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*/
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if (termios->c_iflag & IXON)
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up->efr |= OMAP_UART_SW_TX;
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/*
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* IXOFF Flag:
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* Enable XON/XOFF flow control on input.
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* Receiver compares XON1, XOFF1.
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*/
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if (termios->c_iflag & IXOFF)
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up->efr |= OMAP_UART_SW_RX;
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serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
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up->mcr = serial_in(up, UART_MCR);
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/*
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* IXANY Flag:
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* Enable any character to restart output.
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* Operation resumes after receiving any
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* character after recognition of the XOFF character
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*/
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if (termios->c_iflag & IXANY)
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up->mcr |= UART_MCR_XONANY;
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serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
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serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
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serial_out(up, UART_LCR, up->lcr);
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}
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static void serial_omap_uart_qos_work(struct work_struct *work)
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{
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struct uart_omap_port *up = container_of(work, struct uart_omap_port,
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@@ -726,7 +752,6 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
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{
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struct uart_omap_port *up = to_uart_omap_port(port);
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unsigned char cval = 0;
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unsigned char efr = 0;
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unsigned long flags = 0;
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unsigned int baud, quot;
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@@ -836,11 +861,12 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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up->efr = serial_in(up, UART_EFR);
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up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
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up->efr &= ~UART_EFR_SCD;
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serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
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up->mcr = serial_in(up, UART_MCR);
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up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
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serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
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/* FIFO ENABLE, DMA MODE */
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@@ -859,9 +885,12 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
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serial_out(up, UART_OMAP_SCR, up->scr);
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serial_out(up, UART_EFR, up->efr);
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/* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
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serial_out(up, UART_MCR, up->mcr);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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serial_out(up, UART_EFR, up->efr);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
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/* Protocol, Baud Rate, and Interrupt Settings */
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@@ -871,8 +900,6 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
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serial_out(up, UART_OMAP_MDR1, up->mdr1);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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up->efr = serial_in(up, UART_EFR);
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serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
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serial_out(up, UART_LCR, 0);
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@@ -899,29 +926,68 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
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else
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serial_out(up, UART_OMAP_MDR1, up->mdr1);
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/* Hardware Flow Control Configuration */
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/* Configure flow control */
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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if (termios->c_cflag & CRTSCTS) {
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efr |= (UART_EFR_CTS | UART_EFR_RTS);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
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/* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
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serial_out(up, UART_XON1, termios->c_cc[VSTART]);
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serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
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up->mcr = serial_in(up, UART_MCR);
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serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
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/* Enable access to TCR/TLR */
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serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
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serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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up->efr = serial_in(up, UART_EFR);
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serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
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serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
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serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
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serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
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serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
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serial_out(up, UART_LCR, cval);
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if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
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/* Enable AUTORTS and AUTOCTS */
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up->efr |= UART_EFR_CTS | UART_EFR_RTS;
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/* Ensure MCR RTS is asserted */
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up->mcr |= UART_MCR_RTS;
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} else {
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/* Disable AUTORTS and AUTOCTS */
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up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
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}
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if (up->port.flags & UPF_SOFT_FLOW) {
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/* clear SW control mode bits */
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up->efr &= OMAP_UART_SW_CLR;
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/*
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* IXON Flag:
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* Enable XON/XOFF flow control on input.
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* Receiver compares XON1, XOFF1.
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*/
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if (termios->c_iflag & IXON)
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up->efr |= OMAP_UART_SW_RX;
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/*
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* IXOFF Flag:
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* Enable XON/XOFF flow control on output.
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* Transmit XON1, XOFF1
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*/
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if (termios->c_iflag & IXOFF)
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up->efr |= OMAP_UART_SW_TX;
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/*
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* IXANY Flag:
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* Enable any character to restart output.
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* Operation resumes after receiving any
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* character after recognition of the XOFF character
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*/
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if (termios->c_iflag & IXANY)
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up->mcr |= UART_MCR_XONANY;
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else
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up->mcr &= ~UART_MCR_XONANY;
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}
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serial_out(up, UART_MCR, up->mcr);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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serial_out(up, UART_EFR, up->efr);
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serial_out(up, UART_LCR, up->lcr);
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serial_omap_set_mctrl(&up->port, up->port.mctrl);
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/* Software Flow Control Configuration */
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serial_omap_configure_xonxoff(up, termios);
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spin_unlock_irqrestore(&up->port.lock, flags);
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pm_runtime_mark_last_busy(up->dev);
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@@ -987,6 +1053,7 @@ static void serial_omap_config_port(struct uart_port *port, int flags)
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dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
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up->port.line);
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up->port.type = PORT_OMAP;
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up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
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}
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static int
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@@ -1190,6 +1257,8 @@ static struct uart_ops serial_omap_pops = {
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.get_mctrl = serial_omap_get_mctrl,
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.stop_tx = serial_omap_stop_tx,
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.start_tx = serial_omap_start_tx,
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.throttle = serial_omap_throttle,
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.unthrottle = serial_omap_unthrottle,
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.stop_rx = serial_omap_stop_rx,
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.enable_ms = serial_omap_enable_ms,
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.break_ctl = serial_omap_break_ctl,
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