[SCSI] pm80xx: Firmware logging support.
Supports below logging facilities, Inbound outbound queues dump. Non fatal dump in case of IO failures. Fatal dump in case of firmware failure. [jejb: checkpatch spacing fixes] Signed-off-by: Anandkumar.Santhanam@pmcs.com Reviewed-by: Jack Wang <jinpu.wang@profitbricks.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Šī revīzija ir iekļauta:
Anand Kumar Santhanam
revīziju iesūtīja
James Bottomley
James Bottomley
vecāks
279094079a
revīzija
d078b5117f
@@ -45,6 +45,228 @@
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#define SMP_DIRECT 1
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#define SMP_INDIRECT 2
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int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
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{
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u32 reg_val;
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unsigned long start;
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pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
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/* confirm the setting is written */
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start = jiffies + HZ; /* 1 sec */
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do {
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reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
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} while ((reg_val != shift_value) && time_before(jiffies, start));
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if (reg_val != shift_value) {
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
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" = 0x%x\n", reg_val));
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return -1;
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}
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return 0;
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}
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void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
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const void *destination,
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u32 dw_count, u32 bus_base_number)
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{
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u32 index, value, offset;
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u32 *destination1;
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destination1 = (u32 *)destination;
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for (index = 0; index < dw_count; index += 4, destination1++) {
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offset = (soffset + index / 4);
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if (offset < (64 * 1024)) {
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value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
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*destination1 = cpu_to_le32(value);
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}
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}
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return;
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}
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ssize_t pm80xx_get_fatal_dump(struct device *cdev,
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struct device_attribute *attr, char *buf)
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{
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struct Scsi_Host *shost = class_to_shost(cdev);
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struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
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struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
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void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
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u32 status = 1;
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u32 accum_len , reg_val, index, *temp;
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unsigned long start;
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u8 *direct_data;
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char *fatal_error_data = buf;
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pm8001_ha->forensic_info.data_buf.direct_data = buf;
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if (pm8001_ha->chip_id == chip_8001) {
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
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"Not supported for SPC controller");
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return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
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(char *)buf;
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}
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if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
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PM8001_IO_DBG(pm8001_ha,
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pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
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direct_data = (u8 *)fatal_error_data;
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pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
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pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
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pm8001_ha->forensic_info.data_buf.direct_offset = 0;
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pm8001_ha->forensic_info.data_buf.read_len = 0;
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pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
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}
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if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
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/* start to get data */
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/* Program the MEMBASE II Shifting Register with 0x00.*/
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pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
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pm8001_ha->fatal_forensic_shift_offset);
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pm8001_ha->forensic_last_offset = 0;
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pm8001_ha->forensic_fatal_step = 0;
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pm8001_ha->fatal_bar_loc = 0;
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}
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/* Read until accum_len is retrived */
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accum_len = pm8001_mr32(fatal_table_address,
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MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
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PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
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accum_len));
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if (accum_len == 0xFFFFFFFF) {
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PM8001_IO_DBG(pm8001_ha,
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pm8001_printk("Possible PCI issue 0x%x not expected\n",
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accum_len));
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return status;
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}
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if (accum_len == 0 || accum_len >= 0x100000) {
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
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"%08x ", 0xFFFFFFFF);
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return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
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(char *)buf;
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}
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temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
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if (pm8001_ha->forensic_fatal_step == 0) {
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moreData:
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if (pm8001_ha->forensic_info.data_buf.direct_data) {
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/* Data is in bar, copy to host memory */
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pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
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pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
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pm8001_ha->forensic_info.data_buf.direct_len ,
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1);
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}
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pm8001_ha->fatal_bar_loc +=
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pm8001_ha->forensic_info.data_buf.direct_len;
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pm8001_ha->forensic_info.data_buf.direct_offset +=
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pm8001_ha->forensic_info.data_buf.direct_len;
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pm8001_ha->forensic_last_offset +=
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pm8001_ha->forensic_info.data_buf.direct_len;
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pm8001_ha->forensic_info.data_buf.read_len =
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pm8001_ha->forensic_info.data_buf.direct_len;
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if (pm8001_ha->forensic_last_offset >= accum_len) {
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
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"%08x ", 3);
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for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->
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forensic_info.data_buf.direct_data,
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"%08x ", *(temp + index));
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}
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pm8001_ha->fatal_bar_loc = 0;
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pm8001_ha->forensic_fatal_step = 1;
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pm8001_ha->fatal_forensic_shift_offset = 0;
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pm8001_ha->forensic_last_offset = 0;
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status = 0;
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return (char *)pm8001_ha->
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forensic_info.data_buf.direct_data -
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(char *)buf;
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}
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if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->
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forensic_info.data_buf.direct_data,
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"%08x ", 2);
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for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->
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forensic_info.data_buf.direct_data,
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"%08x ", *(temp + index));
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}
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status = 0;
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return (char *)pm8001_ha->
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forensic_info.data_buf.direct_data -
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(char *)buf;
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}
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/* Increment the MEMBASE II Shifting Register value by 0x100.*/
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
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"%08x ", 2);
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for (index = 0; index < 256; index++) {
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->
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forensic_info.data_buf.direct_data,
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"%08x ", *(temp + index));
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}
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pm8001_ha->fatal_forensic_shift_offset += 0x100;
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pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
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pm8001_ha->fatal_forensic_shift_offset);
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pm8001_ha->fatal_bar_loc = 0;
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status = 0;
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return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
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(char *)buf;
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}
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if (pm8001_ha->forensic_fatal_step == 1) {
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pm8001_ha->fatal_forensic_shift_offset = 0;
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/* Read 64K of the debug data. */
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pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
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pm8001_ha->fatal_forensic_shift_offset);
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pm8001_mw32(fatal_table_address,
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MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
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MPI_FATAL_EDUMP_HANDSHAKE_RDY);
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/* Poll FDDHSHK until clear */
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start = jiffies + (2 * HZ); /* 2 sec */
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do {
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reg_val = pm8001_mr32(fatal_table_address,
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MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
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} while ((reg_val) && time_before(jiffies, start));
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if (reg_val != 0) {
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
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" = 0x%x\n", reg_val));
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return -1;
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}
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/* Read the next 64K of the debug data. */
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pm8001_ha->forensic_fatal_step = 0;
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if (pm8001_mr32(fatal_table_address,
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MPI_FATAL_EDUMP_TABLE_STATUS) !=
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MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
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pm8001_mw32(fatal_table_address,
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MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
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goto moreData;
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} else {
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pm8001_ha->forensic_info.data_buf.direct_data +=
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sprintf(pm8001_ha->
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forensic_info.data_buf.direct_data,
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"%08x ", 4);
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pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
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pm8001_ha->forensic_info.data_buf.direct_len = 0;
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pm8001_ha->forensic_info.data_buf.direct_offset = 0;
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pm8001_ha->forensic_info.data_buf.read_len = 0;
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status = 0;
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}
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}
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return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
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(char *)buf;
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}
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/**
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* read_main_config_table - read the configure table and save it.
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* @pm8001_ha: our hba card information
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@@ -583,6 +805,9 @@ static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
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pm8001_ha->pspa_q_tbl_addr =
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base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
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0xFFFFFF);
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pm8001_ha->fatal_tbl_addr =
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base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
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0xFFFFFF);
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PM8001_INIT_DBG(pm8001_ha,
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pm8001_printk("GST OFFSET 0x%x\n",
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