ASoC: SOF: Intel: hda: use SOF defined init chip in resume
Unify resume code by using SOF common function hda_dsp_ctrl_init_chip() which can handle both HDA and non-HDA cases. Move code to reset stream-to-link mapping into hda_dsp_ctrl_init_chip(). Signed-off-by: Zhu Yingjiang <yingjiang.zhu@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20190722141402.7194-15-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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committed by
Mark Brown

parent
061edb2325
commit
d06973515f
@@ -164,6 +164,9 @@ int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
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int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
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int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
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{
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_bus *bus = sof_to_bus(sdev);
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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struct hdac_ext_link *hlink;
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#endif
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struct hdac_stream *stream;
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struct hdac_stream *stream;
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int sd_offset, ret = 0;
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int sd_offset, ret = 0;
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@@ -253,6 +256,12 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
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upper_32_bits(bus->posbuf.addr));
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upper_32_bits(bus->posbuf.addr));
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}
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* Reset stream-to-link mapping */
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list_for_each_entry(hlink, &bus->hlink_list, list)
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bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
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#endif
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bus->chip_init = true;
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bus->chip_init = true;
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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@@ -368,32 +368,6 @@ static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
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/* check dma status and clean up CORB/RIRB buffers */
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/* check dma status and clean up CORB/RIRB buffers */
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if (!bus->cmd_dma_state)
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if (!bus->cmd_dma_state)
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snd_hdac_bus_stop_cmd_io(bus);
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snd_hdac_bus_stop_cmd_io(bus);
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#else
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hda_dsp_ctrl_misc_clock_gating(sdev, false);
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/* reset controller */
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ret = hda_dsp_ctrl_link_reset(sdev, true);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to reset controller during resume\n");
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return ret;
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}
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/* take controller out of reset */
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ret = hda_dsp_ctrl_link_reset(sdev, false);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: failed to ready controller during resume\n");
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return ret;
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}
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/* enable hda bus irq */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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#endif
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#endif
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/* enable ppcap interrupt */
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/* enable ppcap interrupt */
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