Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates from Olof Johansson: "This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms." Fix up trivial conflicts as per Olof. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits) mfd: vexpress-sysreg: Remove LEDs code irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids irq: versatile: delete dangling variable ARM: sunxi: add missing include for mdelay() ARM: EXYNOS: Avoid early use of of_machine_is_compatible() ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports ARM: S3C24XX: Add clkdev entry for camif-upll clock ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers ARM: sunxi: Add missing sun4i.dtsi file pinctrl: samsung: Do not initialise statics to 0 ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup ...
This commit is contained in:
Linus Torvalds
@@ -18,6 +18,7 @@
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#include <linux/sched.h>
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#include <linux/serial_core.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/export.h>
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#include <linux/irqdomain.h>
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@@ -58,9 +59,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
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static const char name_exynos4212[] = "EXYNOS4212";
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static const char name_exynos4412[] = "EXYNOS4412";
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static const char name_exynos5250[] = "EXYNOS5250";
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static const char name_exynos5440[] = "EXYNOS5440";
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static void exynos4_map_io(void);
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static void exynos5_map_io(void);
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static void exynos5440_map_io(void);
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static void exynos4_init_clocks(int xtal);
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static void exynos5_init_clocks(int xtal);
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static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
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@@ -98,6 +101,12 @@ static struct cpu_table cpu_ids[] __initdata = {
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.init_clocks = exynos5_init_clocks,
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.init = exynos_init,
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.name = name_exynos5250,
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}, {
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.idcode = EXYNOS5440_SOC_ID,
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.idmask = EXYNOS5_SOC_MASK,
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.map_io = exynos5440_map_io,
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.init = exynos_init,
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.name = name_exynos5440,
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},
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};
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@@ -112,6 +121,17 @@ static struct map_desc exynos_iodesc[] __initdata = {
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},
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};
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#ifdef CONFIG_ARCH_EXYNOS5
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static struct map_desc exynos5440_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_CHIPID,
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.pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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#endif
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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@@ -263,6 +283,15 @@ static struct map_desc exynos5_iodesc[] __initdata = {
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},
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};
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static struct map_desc exynos5440_iodesc0[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
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.length = SZ_512K,
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.type = MT_DEVICE,
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},
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};
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void exynos4_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, S5P_SWRESET);
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@@ -270,11 +299,29 @@ void exynos4_restart(char mode, const char *cmd)
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void exynos5_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, EXYNOS_SWRESET);
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u32 val;
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void __iomem *addr;
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if (of_machine_is_compatible("samsung,exynos5250")) {
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val = 0x1;
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addr = EXYNOS_SWRESET;
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} else if (of_machine_is_compatible("samsung,exynos5440")) {
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val = (0x10 << 20) | (0x1 << 16);
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addr = EXYNOS5440_SWRESET;
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} else {
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pr_err("%s: cannot support non-DT\n", __func__);
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return;
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}
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__raw_writel(val, addr);
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}
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void __init exynos_init_late(void)
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{
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if (of_machine_is_compatible("samsung,exynos5440"))
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/* to be supported later */
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return;
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exynos_pm_late_initcall();
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}
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@@ -286,8 +333,20 @@ void __init exynos_init_late(void)
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void __init exynos_init_io(struct map_desc *mach_desc, int size)
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{
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struct map_desc *iodesc = exynos_iodesc;
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int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
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#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
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unsigned long root = of_get_flat_dt_root();
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/* initialize the io descriptors we need for initialization */
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iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
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if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
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iodesc = exynos5440_iodesc;
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iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
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}
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#endif
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iotable_init(iodesc, iodesc_sz);
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if (mach_desc)
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iotable_init(mach_desc, size);
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@@ -356,6 +415,11 @@ static void __init exynos4_init_clocks(int xtal)
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exynos4_setup_clocks();
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}
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static void __init exynos5440_map_io(void)
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{
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iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
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}
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static void __init exynos5_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
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@@ -572,8 +636,9 @@ static int __init combiner_of_init(struct device_node *np,
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return 0;
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}
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static const struct of_device_id exynos4_dt_irq_match[] = {
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static const struct of_device_id exynos_dt_irq_match[] = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
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{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
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{ .compatible = "samsung,exynos4210-combiner",
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.data = combiner_of_init, },
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{},
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@@ -590,7 +655,7 @@ void __init exynos4_init_irq(void)
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gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
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#ifdef CONFIG_OF
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else
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of_irq_init(exynos4_dt_irq_match);
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of_irq_init(exynos_dt_irq_match);
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#endif
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if (!of_have_populated_dt())
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@@ -607,7 +672,7 @@ void __init exynos4_init_irq(void)
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void __init exynos5_init_irq(void)
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{
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#ifdef CONFIG_OF
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of_irq_init(exynos4_dt_irq_match);
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of_irq_init(exynos_dt_irq_match);
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#endif
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/*
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* The parameters of s5p_init_irq() are for VIC init.
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@@ -637,7 +702,7 @@ static int __init exynos4_l2x0_cache_init(void)
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{
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int ret;
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if (soc_is_exynos5250())
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if (soc_is_exynos5250() || soc_is_exynos5440())
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return 0;
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ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
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@@ -968,6 +1033,8 @@ static int __init exynos_init_irq_eint(void)
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}
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}
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#endif
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if (soc_is_exynos5440())
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return 0;
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if (soc_is_exynos5250())
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exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
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