Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates from Olof Johansson: "This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms." Fix up trivial conflicts as per Olof. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits) mfd: vexpress-sysreg: Remove LEDs code irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids irq: versatile: delete dangling variable ARM: sunxi: add missing include for mdelay() ARM: EXYNOS: Avoid early use of of_machine_is_compatible() ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports ARM: S3C24XX: Add clkdev entry for camif-upll clock ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers ARM: sunxi: Add missing sun4i.dtsi file pinctrl: samsung: Do not initialise statics to 0 ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup ...
This commit is contained in:
Linus Torvalds
191
Documentation/devicetree/bindings/clock/imx5-clock.txt
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191
Documentation/devicetree/bindings/clock/imx5-clock.txt
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* Clock bindings for Freescale i.MX5
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Required properties:
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- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
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- reg: Address and length of the register set
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- interrupts: Should contain CCM interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX5
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clocks and IDs.
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Clock ID
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---------------------------
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dummy 0
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ckil 1
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osc 2
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ckih1 3
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ckih2 4
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ahb 5
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ipg 6
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axi_a 7
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axi_b 8
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uart_pred 9
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uart_root 10
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esdhc_a_pred 11
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esdhc_b_pred 12
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esdhc_c_s 13
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esdhc_d_s 14
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emi_sel 15
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emi_slow_podf 16
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nfc_podf 17
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ecspi_pred 18
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ecspi_podf 19
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usboh3_pred 20
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usboh3_podf 21
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usb_phy_pred 22
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usb_phy_podf 23
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cpu_podf 24
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di_pred 25
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tve_di 26
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tve_s 27
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uart1_ipg_gate 28
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uart1_per_gate 29
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uart2_ipg_gate 30
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uart2_per_gate 31
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uart3_ipg_gate 32
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uart3_per_gate 33
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i2c1_gate 34
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i2c2_gate 35
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gpt_ipg_gate 36
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pwm1_ipg_gate 37
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pwm1_hf_gate 38
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pwm2_ipg_gate 39
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pwm2_hf_gate 40
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gpt_hf_gate 41
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fec_gate 42
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usboh3_per_gate 43
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esdhc1_ipg_gate 44
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esdhc2_ipg_gate 45
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esdhc3_ipg_gate 46
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esdhc4_ipg_gate 47
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ssi1_ipg_gate 48
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ssi2_ipg_gate 49
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ssi3_ipg_gate 50
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ecspi1_ipg_gate 51
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ecspi1_per_gate 52
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ecspi2_ipg_gate 53
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ecspi2_per_gate 54
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cspi_ipg_gate 55
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sdma_gate 56
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emi_slow_gate 57
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ipu_s 58
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ipu_gate 59
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nfc_gate 60
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ipu_di1_gate 61
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vpu_s 62
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vpu_gate 63
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vpu_reference_gate 64
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uart4_ipg_gate 65
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uart4_per_gate 66
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uart5_ipg_gate 67
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uart5_per_gate 68
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tve_gate 69
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tve_pred 70
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esdhc1_per_gate 71
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esdhc2_per_gate 72
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esdhc3_per_gate 73
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esdhc4_per_gate 74
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usb_phy_gate 75
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hsi2c_gate 76
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mipi_hsc1_gate 77
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mipi_hsc2_gate 78
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mipi_esc_gate 79
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mipi_hsp_gate 80
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ldb_di1_div_3_5 81
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ldb_di1_div 82
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ldb_di0_div_3_5 83
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ldb_di0_div 84
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ldb_di1_gate 85
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can2_serial_gate 86
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can2_ipg_gate 87
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i2c3_gate 88
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lp_apm 89
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periph_apm 90
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main_bus 91
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ahb_max 92
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aips_tz1 93
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aips_tz2 94
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tmax1 95
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tmax2 96
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tmax3 97
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spba 98
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uart_sel 99
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esdhc_a_sel 100
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esdhc_b_sel 101
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esdhc_a_podf 102
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esdhc_b_podf 103
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ecspi_sel 104
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usboh3_sel 105
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usb_phy_sel 106
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iim_gate 107
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usboh3_gate 108
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emi_fast_gate 109
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ipu_di0_gate 110
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gpc_dvfs 111
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pll1_sw 112
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pll2_sw 113
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pll3_sw 114
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ipu_di0_sel 115
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ipu_di1_sel 116
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tve_ext_sel 117
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mx51_mipi 118
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pll4_sw 119
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ldb_di1_sel 120
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di_pll4_podf 121
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ldb_di0_sel 122
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ldb_di0_gate 123
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usb_phy1_gate 124
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usb_phy2_gate 125
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per_lp_apm 126
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per_pred1 127
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per_pred2 128
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per_podf 129
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per_root 130
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ssi_apm 131
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ssi1_root_sel 132
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ssi2_root_sel 133
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ssi3_root_sel 134
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ssi_ext1_sel 135
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ssi_ext2_sel 136
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ssi_ext1_com_sel 137
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ssi_ext2_com_sel 138
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ssi1_root_pred 139
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ssi1_root_podf 140
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ssi2_root_pred 141
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ssi2_root_podf 142
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ssi_ext1_pred 143
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ssi_ext1_podf 144
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ssi_ext2_pred 145
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ssi_ext2_podf 146
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ssi1_root_gate 147
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ssi2_root_gate 148
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ssi3_root_gate 149
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ssi_ext1_gate 150
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ssi_ext2_gate 151
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epit1_ipg_gate 152
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epit1_hf_gate 153
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epit2_ipg_gate 154
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epit2_hf_gate 155
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can_sel 156
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can1_serial_gate 157
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can1_ipg_gate 158
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Examples (for mx53):
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clks: ccm@53fd4000{
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compatible = "fsl,imx53-ccm";
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reg = <0x53fd4000 0x4000>;
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interrupts = <0 71 0x04 0 72 0x04>;
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#clock-cells = <1>;
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};
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can1: can@53fc8000 {
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compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
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reg = <0x53fc8000 0x4000>;
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interrupts = <82>;
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clocks = <&clks 158>, <&clks 157>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@@ -187,9 +187,9 @@ clocks and IDs.
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pll3_usb_otg 172
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pll4_audio 173
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pll5_video 174
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pll6_mlb 175
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pll8_mlb 175
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pll7_usb_host 176
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pll8_enet 177
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pll6_enet 177
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ssi1_ipg 178
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ssi2_ipg 179
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ssi3_ipg 180
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@@ -198,6 +198,11 @@ clocks and IDs.
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usbphy2 183
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ldb_di0_div_3_5 184
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ldb_di1_div_3_5 185
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sata_ref 186
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sata_ref_100m 187
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pcie_ref 188
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pcie_ref_125m 189
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enet_ref 190
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Examples:
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