Merge branch 'drm-next-analogix-dp-v2' of github.com:yakir-Yang/linux into drm-next
This pull request want to land the analogix_dp driver into drm/bridge directory, which reused the Exynos DP code, and add Rockchip DP support. And those patches have been: * 'drm-next-analogix-dp-v2' of github.com:yakir-Yang/linux: drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time drm: bridge: analogix/dp: add edid modes parse in get_modes method drm: bridge: analogix/dp: move hpd detect to connector detect function drm: bridge: analogix/dp: try force hpd after plug in lookup failed drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 drm: bridge: analogix/dp: add some rk3288 special registers setting dt-bindings: add document for rockchip variant of analogix_dp drm: rockchip: dp: add rockchip platform dp driver ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver dt-bindings: add document for analogix display port driver drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count drm: bridge: analogix/dp: fix some obvious code style drm: bridge: analogix/dp: rename register constants drm/exynos: dp: rename implementation specific driver part drm: bridge: analogix/dp: split exynos dp driver to bridge directory
This commit is contained in:
Dave Airlie
@@ -40,4 +40,6 @@ config DRM_PARADE_PS8622
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---help---
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Parade eDP-LVDS bridge chip driver.
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source "drivers/gpu/drm/bridge/analogix/Kconfig"
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endmenu
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@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
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obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
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obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
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obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
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obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
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3
drivers/gpu/drm/bridge/analogix/Kconfig
Normal file
3
drivers/gpu/drm/bridge/analogix/Kconfig
Normal file
@@ -0,0 +1,3 @@
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config DRM_ANALOGIX_DP
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tristate
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depends on DRM
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2
drivers/gpu/drm/bridge/analogix/Makefile
Normal file
2
drivers/gpu/drm/bridge/analogix/Makefile
Normal file
@@ -0,0 +1,2 @@
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analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o
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obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
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1430
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
Normal file
1430
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
Normal file
File diff suppressed because it is too large
Load Diff
281
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
Normal file
281
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
Normal file
@@ -0,0 +1,281 @@
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/*
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* Header file for Analogix DP (Display Port) core interface driver.
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*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ANALOGIX_DP_CORE_H
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#define _ANALOGIX_DP_CORE_H
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#include <drm/drm_crtc.h>
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#include <drm/drm_dp_helper.h>
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#define DP_TIMEOUT_LOOP_COUNT 100
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#define MAX_CR_LOOP 5
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#define MAX_EQ_LOOP 5
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/* I2C EDID Chip ID, Slave Address */
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#define I2C_EDID_DEVICE_ADDR 0x50
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#define I2C_E_EDID_DEVICE_ADDR 0x30
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#define EDID_BLOCK_LENGTH 0x80
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#define EDID_HEADER_PATTERN 0x00
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#define EDID_EXTENSION_FLAG 0x7e
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#define EDID_CHECKSUM 0x7f
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/* DP_MAX_LANE_COUNT */
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#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
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#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
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/* DP_LANE_COUNT_SET */
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#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
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/* DP_TRAINING_LANE0_SET */
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#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
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#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
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#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
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#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
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enum link_lane_count_type {
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LANE_COUNT1 = 1,
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LANE_COUNT2 = 2,
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LANE_COUNT4 = 4
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};
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enum link_training_state {
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START,
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CLOCK_RECOVERY,
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EQUALIZER_TRAINING,
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FINISHED,
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FAILED
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};
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enum voltage_swing_level {
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VOLTAGE_LEVEL_0,
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VOLTAGE_LEVEL_1,
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VOLTAGE_LEVEL_2,
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VOLTAGE_LEVEL_3,
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};
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enum pre_emphasis_level {
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PRE_EMPHASIS_LEVEL_0,
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PRE_EMPHASIS_LEVEL_1,
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PRE_EMPHASIS_LEVEL_2,
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PRE_EMPHASIS_LEVEL_3,
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};
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enum pattern_set {
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PRBS7,
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D10_2,
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TRAINING_PTN1,
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TRAINING_PTN2,
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DP_NONE
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};
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enum color_space {
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COLOR_RGB,
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COLOR_YCBCR422,
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COLOR_YCBCR444
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};
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enum color_depth {
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COLOR_6,
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COLOR_8,
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COLOR_10,
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COLOR_12
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};
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enum color_coefficient {
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COLOR_YCBCR601,
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COLOR_YCBCR709
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};
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enum dynamic_range {
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VESA,
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CEA
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};
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enum pll_status {
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PLL_UNLOCKED,
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PLL_LOCKED
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};
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enum clock_recovery_m_value_type {
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CALCULATED_M,
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REGISTER_M
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};
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enum video_timing_recognition_type {
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VIDEO_TIMING_FROM_CAPTURE,
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VIDEO_TIMING_FROM_REGISTER
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};
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enum analog_power_block {
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AUX_BLOCK,
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CH0_BLOCK,
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CH1_BLOCK,
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CH2_BLOCK,
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CH3_BLOCK,
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ANALOG_TOTAL,
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POWER_ALL
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};
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enum dp_irq_type {
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DP_IRQ_TYPE_HP_CABLE_IN,
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DP_IRQ_TYPE_HP_CABLE_OUT,
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DP_IRQ_TYPE_HP_CHANGE,
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DP_IRQ_TYPE_UNKNOWN,
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};
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struct video_info {
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char *name;
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bool h_sync_polarity;
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bool v_sync_polarity;
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bool interlaced;
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enum color_space color_space;
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enum dynamic_range dynamic_range;
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enum color_coefficient ycbcr_coeff;
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enum color_depth color_depth;
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int max_link_rate;
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enum link_lane_count_type max_lane_count;
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};
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struct link_train {
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int eq_loop;
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int cr_loop[4];
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u8 link_rate;
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u8 lane_count;
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u8 training_lane[4];
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enum link_training_state lt_state;
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};
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struct analogix_dp_device {
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struct drm_encoder *encoder;
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struct device *dev;
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struct drm_device *drm_dev;
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struct drm_connector connector;
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struct drm_bridge *bridge;
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struct clk *clock;
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unsigned int irq;
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void __iomem *reg_base;
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struct video_info video_info;
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struct link_train link_train;
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struct phy *phy;
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int dpms_mode;
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int hpd_gpio;
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bool force_hpd;
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unsigned char edid[EDID_BLOCK_LENGTH * 2];
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struct analogix_dp_plat_data *plat_data;
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};
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/* analogix_dp_reg.c */
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void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
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void analogix_dp_stop_video(struct analogix_dp_device *dp);
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void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
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void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
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void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
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void analogix_dp_reset(struct analogix_dp_device *dp);
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void analogix_dp_swreset(struct analogix_dp_device *dp);
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void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
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void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp);
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void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp);
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enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
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void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
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void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
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enum analog_power_block block,
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bool enable);
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void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
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void analogix_dp_init_hpd(struct analogix_dp_device *dp);
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void analogix_dp_force_hpd(struct analogix_dp_device *dp);
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enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
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void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
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void analogix_dp_reset_aux(struct analogix_dp_device *dp);
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void analogix_dp_init_aux(struct analogix_dp_device *dp);
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int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
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void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
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int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
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int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
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unsigned int reg_addr,
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unsigned char data);
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int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
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unsigned int reg_addr,
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unsigned char *data);
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int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char data[]);
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int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char data[]);
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int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr);
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int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr,
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unsigned int *data);
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int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
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unsigned int device_addr,
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unsigned int reg_addr,
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unsigned int count,
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unsigned char edid[]);
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void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
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void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
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void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
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void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
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void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
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bool enable);
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void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
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enum pattern_set pattern);
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void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
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u32 level);
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void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
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u32 level);
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void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
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u32 level);
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void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
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u32 level);
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void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
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u32 training_lane);
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void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
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u32 training_lane);
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void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
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u32 training_lane);
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void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
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u32 training_lane);
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u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
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u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
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u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
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u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
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void analogix_dp_reset_macro(struct analogix_dp_device *dp);
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void analogix_dp_init_video(struct analogix_dp_device *dp);
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void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
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int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
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void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
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enum clock_recovery_m_value_type type,
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u32 m_value,
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u32 n_value);
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void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
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void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
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bool enable);
|
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void analogix_dp_start_video(struct analogix_dp_device *dp);
|
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int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
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void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
|
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void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
|
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void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
|
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#endif /* _ANALOGIX_DP_CORE_H */
|
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1320
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
Normal file
1320
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
Normal file
File diff suppressed because it is too large
Load Diff
378
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
Normal file
378
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
Normal file
@@ -0,0 +1,378 @@
|
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/*
|
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* Register definition file for Analogix DP core driver
|
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*
|
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
|
||||
* Author: Jingoo Han <jg1.han@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
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|
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#ifndef _ANALOGIX_DP_REG_H
|
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#define _ANALOGIX_DP_REG_H
|
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|
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#define ANALOGIX_DP_TX_SW_RESET 0x14
|
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#define ANALOGIX_DP_FUNC_EN_1 0x18
|
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#define ANALOGIX_DP_FUNC_EN_2 0x1C
|
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#define ANALOGIX_DP_VIDEO_CTL_1 0x20
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#define ANALOGIX_DP_VIDEO_CTL_2 0x24
|
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#define ANALOGIX_DP_VIDEO_CTL_3 0x28
|
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|
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#define ANALOGIX_DP_VIDEO_CTL_8 0x3C
|
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#define ANALOGIX_DP_VIDEO_CTL_10 0x44
|
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|
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#define ANALOGIX_DP_PLL_REG_1 0xfc
|
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#define ANALOGIX_DP_PLL_REG_2 0x9e4
|
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#define ANALOGIX_DP_PLL_REG_3 0x9e8
|
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#define ANALOGIX_DP_PLL_REG_4 0x9ec
|
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#define ANALOGIX_DP_PLL_REG_5 0xa00
|
||||
|
||||
#define ANALOGIX_DP_PD 0x12c
|
||||
|
||||
#define ANALOGIX_DP_LANE_MAP 0x35C
|
||||
|
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#define ANALOGIX_DP_ANALOG_CTL_1 0x370
|
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#define ANALOGIX_DP_ANALOG_CTL_2 0x374
|
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#define ANALOGIX_DP_ANALOG_CTL_3 0x378
|
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#define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C
|
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#define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380
|
||||
|
||||
#define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390
|
||||
|
||||
#define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4
|
||||
#define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8
|
||||
#define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC
|
||||
#define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0
|
||||
#define ANALOGIX_DP_INT_STA 0x3DC
|
||||
#define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0
|
||||
#define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4
|
||||
#define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8
|
||||
#define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC
|
||||
#define ANALOGIX_DP_INT_STA_MASK 0x3F8
|
||||
#define ANALOGIX_DP_INT_CTL 0x3FC
|
||||
|
||||
#define ANALOGIX_DP_SYS_CTL_1 0x600
|
||||
#define ANALOGIX_DP_SYS_CTL_2 0x604
|
||||
#define ANALOGIX_DP_SYS_CTL_3 0x608
|
||||
#define ANALOGIX_DP_SYS_CTL_4 0x60C
|
||||
|
||||
#define ANALOGIX_DP_PKT_SEND_CTL 0x640
|
||||
#define ANALOGIX_DP_HDCP_CTL 0x648
|
||||
|
||||
#define ANALOGIX_DP_LINK_BW_SET 0x680
|
||||
#define ANALOGIX_DP_LANE_COUNT_SET 0x684
|
||||
#define ANALOGIX_DP_TRAINING_PTN_SET 0x688
|
||||
#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C
|
||||
#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690
|
||||
#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694
|
||||
#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698
|
||||
|
||||
#define ANALOGIX_DP_DEBUG_CTL 0x6C0
|
||||
#define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4
|
||||
#define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8
|
||||
#define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0
|
||||
|
||||
#define ANALOGIX_DP_M_VID_0 0x700
|
||||
#define ANALOGIX_DP_M_VID_1 0x704
|
||||
#define ANALOGIX_DP_M_VID_2 0x708
|
||||
#define ANALOGIX_DP_N_VID_0 0x70C
|
||||
#define ANALOGIX_DP_N_VID_1 0x710
|
||||
#define ANALOGIX_DP_N_VID_2 0x714
|
||||
|
||||
#define ANALOGIX_DP_PLL_CTL 0x71C
|
||||
#define ANALOGIX_DP_PHY_PD 0x720
|
||||
#define ANALOGIX_DP_PHY_TEST 0x724
|
||||
|
||||
#define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730
|
||||
#define ANALOGIX_DP_AUDIO_MARGIN 0x73C
|
||||
|
||||
#define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764
|
||||
#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778
|
||||
#define ANALOGIX_DP_AUX_CH_STA 0x780
|
||||
#define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788
|
||||
#define ANALOGIX_DP_AUX_RX_COMM 0x78C
|
||||
#define ANALOGIX_DP_BUFFER_DATA_CTL 0x790
|
||||
#define ANALOGIX_DP_AUX_CH_CTL_1 0x794
|
||||
#define ANALOGIX_DP_AUX_ADDR_7_0 0x798
|
||||
#define ANALOGIX_DP_AUX_ADDR_15_8 0x79C
|
||||
#define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0
|
||||
#define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4
|
||||
|
||||
#define ANALOGIX_DP_BUF_DATA_0 0x7C0
|
||||
|
||||
#define ANALOGIX_DP_SOC_GENERAL_CTL 0x800
|
||||
|
||||
/* ANALOGIX_DP_TX_SW_RESET */
|
||||
#define RESET_DP_TX (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_FUNC_EN_1 */
|
||||
#define MASTER_VID_FUNC_EN_N (0x1 << 7)
|
||||
#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
|
||||
#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
|
||||
#define AUD_FUNC_EN_N (0x1 << 3)
|
||||
#define HDCP_FUNC_EN_N (0x1 << 2)
|
||||
#define CRC_FUNC_EN_N (0x1 << 1)
|
||||
#define SW_FUNC_EN_N (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_FUNC_EN_2 */
|
||||
#define SSC_FUNC_EN_N (0x1 << 7)
|
||||
#define AUX_FUNC_EN_N (0x1 << 2)
|
||||
#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
|
||||
#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_VIDEO_CTL_1 */
|
||||
#define VIDEO_EN (0x1 << 7)
|
||||
#define HDCP_VIDEO_MUTE (0x1 << 6)
|
||||
|
||||
/* ANALOGIX_DP_VIDEO_CTL_1 */
|
||||
#define IN_D_RANGE_MASK (0x1 << 7)
|
||||
#define IN_D_RANGE_SHIFT (7)
|
||||
#define IN_D_RANGE_CEA (0x1 << 7)
|
||||
#define IN_D_RANGE_VESA (0x0 << 7)
|
||||
#define IN_BPC_MASK (0x7 << 4)
|
||||
#define IN_BPC_SHIFT (4)
|
||||
#define IN_BPC_12_BITS (0x3 << 4)
|
||||
#define IN_BPC_10_BITS (0x2 << 4)
|
||||
#define IN_BPC_8_BITS (0x1 << 4)
|
||||
#define IN_BPC_6_BITS (0x0 << 4)
|
||||
#define IN_COLOR_F_MASK (0x3 << 0)
|
||||
#define IN_COLOR_F_SHIFT (0)
|
||||
#define IN_COLOR_F_YCBCR444 (0x2 << 0)
|
||||
#define IN_COLOR_F_YCBCR422 (0x1 << 0)
|
||||
#define IN_COLOR_F_RGB (0x0 << 0)
|
||||
|
||||
/* ANALOGIX_DP_VIDEO_CTL_3 */
|
||||
#define IN_YC_COEFFI_MASK (0x1 << 7)
|
||||
#define IN_YC_COEFFI_SHIFT (7)
|
||||
#define IN_YC_COEFFI_ITU709 (0x1 << 7)
|
||||
#define IN_YC_COEFFI_ITU601 (0x0 << 7)
|
||||
#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
|
||||
#define VID_CHK_UPDATE_TYPE_SHIFT (4)
|
||||
#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
|
||||
#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
|
||||
|
||||
/* ANALOGIX_DP_VIDEO_CTL_8 */
|
||||
#define VID_HRES_TH(x) (((x) & 0xf) << 4)
|
||||
#define VID_VRES_TH(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* ANALOGIX_DP_VIDEO_CTL_10 */
|
||||
#define FORMAT_SEL (0x1 << 4)
|
||||
#define INTERACE_SCAN_CFG (0x1 << 2)
|
||||
#define VSYNC_POLARITY_CFG (0x1 << 1)
|
||||
#define HSYNC_POLARITY_CFG (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_PLL_REG_1 */
|
||||
#define REF_CLK_24M (0x1 << 1)
|
||||
#define REF_CLK_27M (0x0 << 1)
|
||||
|
||||
/* ANALOGIX_DP_LANE_MAP */
|
||||
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
|
||||
#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
|
||||
#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
|
||||
#define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6)
|
||||
#define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4)
|
||||
#define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
|
||||
#define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
|
||||
#define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4)
|
||||
#define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2)
|
||||
#define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
|
||||
#define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
|
||||
#define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2)
|
||||
#define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0)
|
||||
#define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
|
||||
#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
|
||||
#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
|
||||
|
||||
/* ANALOGIX_DP_ANALOG_CTL_1 */
|
||||
#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4)
|
||||
|
||||
/* ANALOGIX_DP_ANALOG_CTL_2 */
|
||||
#define SEL_24M (0x1 << 3)
|
||||
#define TX_DVDD_BIT_1_0625V (0x4 << 0)
|
||||
|
||||
/* ANALOGIX_DP_ANALOG_CTL_3 */
|
||||
#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
|
||||
#define VCO_BIT_600_MICRO (0x5 << 0)
|
||||
|
||||
/* ANALOGIX_DP_PLL_FILTER_CTL_1 */
|
||||
#define PD_RING_OSC (0x1 << 6)
|
||||
#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
|
||||
#define TX_CUR1_2X (0x1 << 2)
|
||||
#define TX_CUR_16_MA (0x3 << 0)
|
||||
|
||||
/* ANALOGIX_DP_TX_AMP_TUNING_CTL */
|
||||
#define CH3_AMP_400_MV (0x0 << 24)
|
||||
#define CH2_AMP_400_MV (0x0 << 16)
|
||||
#define CH1_AMP_400_MV (0x0 << 8)
|
||||
#define CH0_AMP_400_MV (0x0 << 0)
|
||||
|
||||
/* ANALOGIX_DP_AUX_HW_RETRY_CTL */
|
||||
#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
|
||||
#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
|
||||
#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
|
||||
#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
|
||||
#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
|
||||
#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
|
||||
#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
|
||||
|
||||
/* ANALOGIX_DP_COMMON_INT_STA_1 */
|
||||
#define VSYNC_DET (0x1 << 7)
|
||||
#define PLL_LOCK_CHG (0x1 << 6)
|
||||
#define SPDIF_ERR (0x1 << 5)
|
||||
#define SPDIF_UNSTBL (0x1 << 4)
|
||||
#define VID_FORMAT_CHG (0x1 << 3)
|
||||
#define AUD_CLK_CHG (0x1 << 2)
|
||||
#define VID_CLK_CHG (0x1 << 1)
|
||||
#define SW_INT (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_COMMON_INT_STA_2 */
|
||||
#define ENC_EN_CHG (0x1 << 6)
|
||||
#define HW_BKSV_RDY (0x1 << 3)
|
||||
#define HW_SHA_DONE (0x1 << 2)
|
||||
#define HW_AUTH_STATE_CHG (0x1 << 1)
|
||||
#define HW_AUTH_DONE (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_COMMON_INT_STA_3 */
|
||||
#define AFIFO_UNDER (0x1 << 7)
|
||||
#define AFIFO_OVER (0x1 << 6)
|
||||
#define R0_CHK_FLAG (0x1 << 5)
|
||||
|
||||
/* ANALOGIX_DP_COMMON_INT_STA_4 */
|
||||
#define PSR_ACTIVE (0x1 << 7)
|
||||
#define PSR_INACTIVE (0x1 << 6)
|
||||
#define SPDIF_BI_PHASE_ERR (0x1 << 5)
|
||||
#define HOTPLUG_CHG (0x1 << 2)
|
||||
#define HPD_LOST (0x1 << 1)
|
||||
#define PLUG (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_INT_STA */
|
||||
#define INT_HPD (0x1 << 6)
|
||||
#define HW_TRAINING_FINISH (0x1 << 5)
|
||||
#define RPLY_RECEIV (0x1 << 1)
|
||||
#define AUX_ERR (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_INT_CTL */
|
||||
#define SOFT_INT_CTRL (0x1 << 2)
|
||||
#define INT_POL1 (0x1 << 1)
|
||||
#define INT_POL0 (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_SYS_CTL_1 */
|
||||
#define DET_STA (0x1 << 2)
|
||||
#define FORCE_DET (0x1 << 1)
|
||||
#define DET_CTRL (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_SYS_CTL_2 */
|
||||
#define CHA_CRI(x) (((x) & 0xf) << 4)
|
||||
#define CHA_STA (0x1 << 2)
|
||||
#define FORCE_CHA (0x1 << 1)
|
||||
#define CHA_CTRL (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_SYS_CTL_3 */
|
||||
#define HPD_STATUS (0x1 << 6)
|
||||
#define F_HPD (0x1 << 5)
|
||||
#define HPD_CTRL (0x1 << 4)
|
||||
#define HDCP_RDY (0x1 << 3)
|
||||
#define STRM_VALID (0x1 << 2)
|
||||
#define F_VALID (0x1 << 1)
|
||||
#define VALID_CTRL (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_SYS_CTL_4 */
|
||||
#define FIX_M_AUD (0x1 << 4)
|
||||
#define ENHANCED (0x1 << 3)
|
||||
#define FIX_M_VID (0x1 << 2)
|
||||
#define M_VID_UPDATE_CTRL (0x3 << 0)
|
||||
|
||||
/* ANALOGIX_DP_TRAINING_PTN_SET */
|
||||
#define SCRAMBLER_TYPE (0x1 << 9)
|
||||
#define HW_LINK_TRAINING_PATTERN (0x1 << 8)
|
||||
#define SCRAMBLING_DISABLE (0x1 << 5)
|
||||
#define SCRAMBLING_ENABLE (0x0 << 5)
|
||||
#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
|
||||
#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
|
||||
#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
|
||||
#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
|
||||
#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
|
||||
#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
|
||||
#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
|
||||
#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
|
||||
|
||||
/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
|
||||
#define PRE_EMPHASIS_SET_MASK (0x3 << 3)
|
||||
#define PRE_EMPHASIS_SET_SHIFT (3)
|
||||
|
||||
/* ANALOGIX_DP_DEBUG_CTL */
|
||||
#define PLL_LOCK (0x1 << 4)
|
||||
#define F_PLL_LOCK (0x1 << 3)
|
||||
#define PLL_LOCK_CTRL (0x1 << 2)
|
||||
#define PN_INV (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_PLL_CTL */
|
||||
#define DP_PLL_PD (0x1 << 7)
|
||||
#define DP_PLL_RESET (0x1 << 6)
|
||||
#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
|
||||
#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
|
||||
#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
|
||||
|
||||
/* ANALOGIX_DP_PHY_PD */
|
||||
#define DP_PHY_PD (0x1 << 5)
|
||||
#define AUX_PD (0x1 << 4)
|
||||
#define CH3_PD (0x1 << 3)
|
||||
#define CH2_PD (0x1 << 2)
|
||||
#define CH1_PD (0x1 << 1)
|
||||
#define CH0_PD (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_PHY_TEST */
|
||||
#define MACRO_RST (0x1 << 5)
|
||||
#define CH1_TEST (0x1 << 1)
|
||||
#define CH0_TEST (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_AUX_CH_STA */
|
||||
#define AUX_BUSY (0x1 << 4)
|
||||
#define AUX_STATUS_MASK (0xf << 0)
|
||||
|
||||
/* ANALOGIX_DP_AUX_CH_DEFER_CTL */
|
||||
#define DEFER_CTRL_EN (0x1 << 7)
|
||||
#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
|
||||
|
||||
/* ANALOGIX_DP_AUX_RX_COMM */
|
||||
#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
|
||||
#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
|
||||
|
||||
/* ANALOGIX_DP_BUFFER_DATA_CTL */
|
||||
#define BUF_CLR (0x1 << 7)
|
||||
#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
|
||||
|
||||
/* ANALOGIX_DP_AUX_CH_CTL_1 */
|
||||
#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
|
||||
#define AUX_TX_COMM_MASK (0xf << 0)
|
||||
#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
|
||||
#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
|
||||
#define AUX_TX_COMM_MOT (0x1 << 2)
|
||||
#define AUX_TX_COMM_WRITE (0x0 << 0)
|
||||
#define AUX_TX_COMM_READ (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_AUX_ADDR_7_0 */
|
||||
#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
|
||||
|
||||
/* ANALOGIX_DP_AUX_ADDR_15_8 */
|
||||
#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
|
||||
|
||||
/* ANALOGIX_DP_AUX_ADDR_19_16 */
|
||||
#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
|
||||
|
||||
/* ANALOGIX_DP_AUX_CH_CTL_2 */
|
||||
#define ADDR_ONLY (0x1 << 1)
|
||||
#define AUX_EN (0x1 << 0)
|
||||
|
||||
/* ANALOGIX_DP_SOC_GENERAL_CTL */
|
||||
#define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
|
||||
#define AUDIO_MODE_MASTER_MODE (0x0 << 8)
|
||||
#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
|
||||
#define VIDEO_MASTER_CLK_SEL (0x1 << 2)
|
||||
#define VIDEO_MASTER_MODE_EN (0x1 << 1)
|
||||
#define VIDEO_MODE_MASK (0x1 << 0)
|
||||
#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
|
||||
#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
|
||||
|
||||
#endif /* _ANALOGIX_DP_REG_H */
|
||||
Reference in New Issue
Block a user