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mtd: nand: jz4740: Let the pinctrl driver configure the pins

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Before, this NAND driver would set itself the configuration of the
chip-select pins for the various NAND banks.

Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Paul Cercueil
2017-05-12 18:53:04 +02:00
committed by Linus Walleij
parent 695ff98577
commit cf2fd519e6
1 changed files with 1 additions and 22 deletions
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23
drivers/mtd/nand/jz4740_nand.c
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@@ -25,7 +25,6 @@
#include <linux/gpio.h> #include <linux/gpio.h>
#include <asm/mach-jz4740/gpio.h>
#include <asm/mach-jz4740/jz4740_nand.h> #include <asm/mach-jz4740/jz4740_nand.h>
#define JZ_REG_NAND_CTRL 0x50 #define JZ_REG_NAND_CTRL 0x50
@@ -310,34 +309,20 @@ static int jz_nand_detect_bank(struct platform_device *pdev,
uint8_t *nand_dev_id) uint8_t *nand_dev_id)
{ {
int ret; int ret;
int gpio;
char gpio_name[9];
char res_name[6]; char res_name[6];
uint32_t ctrl; uint32_t ctrl;
struct nand_chip *chip = &nand->chip; struct nand_chip *chip = &nand->chip;
struct mtd_info *mtd = nand_to_mtd(chip); struct mtd_info *mtd = nand_to_mtd(chip);
/* Request GPIO port. */
gpio = JZ_GPIO_MEM_CS0 + bank - 1;
sprintf(gpio_name, "NAND CS%d", bank);
ret = gpio_request(gpio, gpio_name);
if (ret) {
dev_warn(&pdev->dev,
"Failed to request %s gpio %d: %d\n",
gpio_name, gpio, ret);
goto notfound_gpio;
}
/* Request I/O resource. */ /* Request I/O resource. */
sprintf(res_name, "bank%d", bank); sprintf(res_name, "bank%d", bank);
ret = jz_nand_ioremap_resource(pdev, res_name, ret = jz_nand_ioremap_resource(pdev, res_name,
&nand->bank_mem[bank - 1], &nand->bank_mem[bank - 1],
&nand->bank_base[bank - 1]); &nand->bank_base[bank - 1]);
if (ret) if (ret)
goto notfound_resource; return ret;
/* Enable chip in bank. */ /* Enable chip in bank. */
jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
ctrl = readl(nand->base + JZ_REG_NAND_CTRL); ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1); ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
writel(ctrl, nand->base + JZ_REG_NAND_CTRL); writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
@@ -377,12 +362,8 @@ notfound_id:
dev_info(&pdev->dev, "No chip found on bank %i\n", bank); dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1)); ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
writel(ctrl, nand->base + JZ_REG_NAND_CTRL); writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
jz_nand_iounmap_resource(nand->bank_mem[bank - 1], jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]); nand->bank_base[bank - 1]);
notfound_resource:
gpio_free(gpio);
notfound_gpio:
return ret; return ret;
} }
@@ -503,7 +484,6 @@ err_nand_release:
err_unclaim_banks: err_unclaim_banks:
while (chipnr--) { while (chipnr--) {
unsigned char bank = nand->banks[chipnr]; unsigned char bank = nand->banks[chipnr];
gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
jz_nand_iounmap_resource(nand->bank_mem[bank - 1], jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]); nand->bank_base[bank - 1]);
} }
@@ -530,7 +510,6 @@ static int jz_nand_remove(struct platform_device *pdev)
if (bank != 0) { if (bank != 0) {
jz_nand_iounmap_resource(nand->bank_mem[bank - 1], jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
nand->bank_base[bank - 1]); nand->bank_base[bank - 1]);
gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
} }
} }