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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Browse Source 
Pull ARM DT updates from Arnd Bergmann:
 "This is another huge branch with close to 450 changessets related to
  devicetree files, roughly half of this for 32-bit and 64-bit
  respectively. There are lots of cleanups and additional hardware
  support for platforms we already support based on SoCs from Renesas,
  ST-Microelectronics, Intel/Altera, Rockchips, Allwinner, Broadcom and
  other manufacturers.

  A total of 6 new SoCs and 37 new boards gets added this time, one more
  SoC will come in a follow-up branch. Most of the new boards are for
  64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7.

  Going more into details for SoC platforms with new hardware support:

   - The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone
     platform, usually paired with an external 5G modem. So far we only
     support the Qualcomm SM8150 MTP reference platform, but no actual
     products.

   - For the slightly older Qualcomm platforms, support for several
     interesting products is getting added: Three laptops based on
     Snapdragon 835/MSM8998 (Asus NovaGo, HP Envy X2 and Lenovo Miix
     630), one laptop based on Snapdragon 850/sdm850 (Lenovo Yoga C630)
     and several phones based on the older Snapdragon 410/MSM8916
     (Samsung A3 and A5, Longcheer L8150 aka Android One 2nd gen "seed"
     aka Wileyfox Swift).

   - Mediatek MT7629 is a new wireless network router chip, similar to
     the older MT7623. It gets added together with the reference board
     implementation.

   - Allwinner V3 is a repackaged version of the existing low-end V3s
     chip, and is used in the tiny Lichee Pi Zero plus, also added here.
     There is also a new TV set-top box based on Allwinner H6, the Tanix
     TX6, and the eMMC variant of the Olimex A64-Olinuxino development
     board.

   - NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC
     family, similar to the i.MX8M Mini. As usual, there is a large
     number of new boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML,
     SolidRun Hummingboard Pulse baseboard and System-on-Module,
     Boundary Devices i.MX8MQ Nitrogen8M, and TechNexion
     PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit, we get the
     Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC
     phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight
     Innovations i.MX7 RMU2 board.

   - In a different NXP product line, the Layerscape LS1046A "Freeway"
     reference board gets added.

   - Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from
     their set-top-box line and smart speaker with newer CPU and GPU
     cores compared to their predecessors. Both are now also supported
     by the Khadas VIM3 development board series, and the dts files for
     that get reorganized a bit to better deal with all variants.
     Another board based on SM1 that gets added is the SEI Robotics
     SEI610.

   - There are a handful of new x86 and Power9 server boards using
     Aspeed BMC chips that are gaining support for running Linux on the
     BMC through the OpenBMC project: Facebook
     Minipack/Wedge100/Wedge40, Lenovo Hr855xg2, and Mihawk. Notably
     these are still new machines using SoCs based on the ARM9 and ARM11
     CPU cores, as support for the new Cortex-A7 based AST2600 is still
     ramping up.

   - There are three new end-user products using 32-bit Rockchips SoCs:
     Mecer Xtreme Mini S6 is an Android "mini PC" box based on the
     low-end RK3229 chip, while the two AOpen products Chromebox Mini
     (Fievel) and Chromebase Mini (Tiger) run ChromeOS and are meant for
     commercial settings(digital signage, PoS, ...).

   - One more single-board computer based on the popular 64-bit RK3399
     is added: the Leez RK3399 P710"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (467 commits)
  arm64: dts: qcom: Add Lenovo Yoga C630
  ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit
  ARM; dts: aspeed: mihawk: File should not be executable
  ARM: dts: aspeed: swift: Change power supplies to version 2
  ARM: dts: aspeed: vesnin: Add secondary SPI flash chip
  ARM: dts: aspeed: vesnin: Add wdt2 with alt-boot option
  ARM: dts: aspeed-g4: Add all flash chips
  ARM: dts: exynos: Enable GPU/Mali T604 on Arndale board
  ARM: dts: exynos: Enable GPU/Mali T604 on Chromebook Snow
  ARM: dts: exynos: Add GPU/Mali T604 node to Exynos5250
  ARM: dts: exynos: Fix min/max buck4 for GPU on Arndale board
  ARM: dts: exynos: Mark LDO10 as always-on on Peach Pit/Pi Chromebooks
  ARM: dts: exynos: Remove not accurate secondary ADC compatible
  arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
  arm64: dts: meson-sm1-sei610: add stdout-path property back
  arm64: dts: meson-sm1-sei610: enable DVFS
  arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
  dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings
  arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
  arm64: dts: meson: g12a: add reset to tdm formatters
  ...
This commit is contained in:
Linus Torvalds
2019-09-16 15:56:22 -07:00
parent d47ebd6842 44acee2078
commit cef7298262
421 changed files with 27990 additions and 7927 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
arch/arm/boot/dts/Makefile
View File

@@ -569,17 +569,22 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-geam.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
imx6ul-kontron-n6310-s.dtb \
imx6ul-kontron-n6310-s-43.dtb \
imx6ul-liteboard.dtb \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
imx6ul-phytec-phyboard-segin-full.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-phytec-segin-lc-rdk-nand.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
@@ -594,6 +599,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb.dtb \
imx7d-sdb-reva.dtb \
imx7d-sdb-sht11.dtb \
imx7d-zii-rmu2.dtb \
imx7d-zii-rpu2.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-mba7.dtb \
@@ -905,9 +911,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
rk3229-evb.dtb \
rk3229-xms6.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
rk3288-fennec.dtb \
rk3288-firefly-beta.dtb \
rk3288-firefly.dtb \
rk3288-firefly-reload.dtb \
@@ -919,6 +925,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
rk3288-veyron-brain.dtb \
rk3288-veyron-fievel.dtb \
rk3288-veyron-jaq.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
@@ -926,6 +933,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
rk3288-veyron-speedy.dtb \
rk3288-veyron-tiger.dtb \
rk3288-vyasa.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
@@ -1114,6 +1122,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-s3-lichee-zero-plus.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
@@ -1262,6 +1271,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623a-rfb-nand.dtb \
mt7623n-rfb-emmc.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
@@ -1271,13 +1281,18 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-facebook-cmm.dtb \
aspeed-bmc-facebook-minipack.dtb \
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-facebook-wedge40.dtb \
aspeed-bmc-facebook-wedge100.dtb \
aspeed-bmc-facebook-yamp.dtb \
aspeed-bmc-intel-s2600wf.dtb \
aspeed-bmc-inspur-fp5280g2.dtb \
aspeed-bmc-lenovo-hr630.dtb \
aspeed-bmc-lenovo-hr855xg2.dtb \
aspeed-bmc-microsoft-olympus.dtb \
aspeed-bmc-opp-lanyang.dtb \
aspeed-bmc-opp-mihawk.dtb \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
aspeed-bmc-opp-swift.dtb \

92
arch/arm/boot/dts/am335x-boneblue.dts
View File

@@ -5,23 +5,13 @@
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-osd335x-common.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TI AM335x BeagleBone Blue";
compatible = "ti,am335x-bone-blue", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
chosen {
stdout-path = &uart0;
};
@@ -142,13 +132,6 @@
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */
@@ -328,16 +311,6 @@
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 {
reg = <0x24>;
};
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
@@ -381,66 +354,13 @@
/include/ "tps65217.dtsi"
&tps {
interrupts = <7>; /* NMI */
interrupt-parent = <&intc>;
/delete-property/ ti,pmic-shutdown-controller;
charger {
interrupts = <0>, <1>;
interrupt-names = "USB", "AC";
status = "okay";
};
pwrbutton {
interrupts = <2>;
status = "okay";
};
regulators {
dcdc1_reg: regulator@0 {
regulator-name = "vdds_dpr";
regulator-always-on;
};
dcdc2_reg: regulator@1 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};
dcdc3_reg: regulator@2 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
regulator-name = "vio,vrtc,vdds";
regulator-always-on;
};
ldo2_reg: regulator@4 {
regulator-name = "vdd_3v3aux";
regulator-always-on;
};
ldo3_reg: regulator@5 {
regulator-name = "vdd_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: regulator@6 {
regulator-name = "vdd_3v3a";
regulator-always-on;
};
};
};
&mmc1 {
@@ -502,14 +422,6 @@
};
};
&aes {
status = "okay";
};
&sham {
status = "okay";
};
&rtc {
system-power-controller;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;

1
arch/arm/boot/dts/am335x-cm-t335.dts
View File

@@ -44,7 +44,6 @@
regulator-name = "vwlan_fixed";
gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */
enable-active-high;
regulator-boot-off;
};
backlight {

11
arch/arm/boot/dts/aspeed-ast2500-evb.dts
View File

@@ -94,6 +94,17 @@
};
};
&sdmmc {
status = "okay";
};
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1_default>;
};
/*
* Enable port A as device (via the virtual hub) and port B as
* host by default on the eval board. This can be easily changed

429
arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts Normal file
View File

@@ -0,0 +1,429 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
#include "aspeed-g5.dtsi"
/ {
model = "Facebook Minipack 100 BMC";
compatible = "facebook,minipack-bmc", "aspeed,ast2500";
aliases {
/*
* Override the default serial aliases to avoid breaking
* the legacy applications.
*/
serial0 = &uart5;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
/*
* i2c switch 2-0070, pca9548, 8 child channels assigned
* with bus number 16-23.
*/
i2c16 = &imux16;
i2c17 = &imux17;
i2c18 = &imux18;
i2c19 = &imux19;
i2c20 = &imux20;
i2c21 = &imux21;
i2c22 = &imux22;
i2c23 = &imux23;
/*
* i2c switch 8-0070, pca9548, 8 child channels assigned
* with bus number 24-31.
*/
i2c24 = &imux24;
i2c25 = &imux25;
i2c26 = &imux26;
i2c27 = &imux27;
i2c28 = &imux28;
i2c29 = &imux29;
i2c30 = &imux30;
i2c31 = &imux31;
/*
* i2c switch 9-0070, pca9548, 8 child channels assigned
* with bus number 32-39.
*/
i2c32 = &imux32;
i2c33 = &imux33;
i2c34 = &imux34;
i2c35 = &imux35;
i2c36 = &imux36;
i2c37 = &imux37;
i2c38 = &imux38;
i2c39 = &imux39;
/*
* i2c switch 11-0070, pca9548, 8 child channels assigned
* with bus number 40-47.
*/
i2c40 = &imux40;
i2c41 = &imux41;
i2c42 = &imux42;
i2c43 = &imux43;
i2c44 = &imux44;
i2c45 = &imux45;
i2c46 = &imux46;
i2c47 = &imux47;
};
chosen {
stdout-path = &uart1;
bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
&wdt1 {
status = "okay";
aspeed,reset-type = "system";
};
&wdt2 {
status = "okay";
aspeed,reset-type = "system";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
#include "facebook-bmc-flash-layout.dtsi"
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_ncts1_default
&pinctrl_ndsr1_default
&pinctrl_ndtr1_default
&pinctrl_nrts1_default>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default
&pinctrl_rxd2_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
&pinctrl_rxd4_default>;
};
&uart5 {
status = "okay";
};
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
bus-frequency = <400000>;
multi-master;
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
imux16: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux17: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux18: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux19: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux20: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux21: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux22: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux23: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
multi-master;
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
imux24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux26: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux27: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux28: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux29: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux30: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux31: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&i2c9 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
imux32: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux33: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux34: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux35: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux36: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux37: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux38: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux39: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
imux40: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux41: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux42: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux43: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux44: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux45: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux46: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux47: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&vhub {
status = "okay";
};

272
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
View File

@@ -12,6 +12,27 @@
aliases {
serial0 = &uart1;
serial4 = &uart5;
/*
* Hardcode the bus number of i2c switches' channels to
* avoid breaking the legacy applications.
*/
i2c16 = &imux16;
i2c17 = &imux17;
i2c18 = &imux18;
i2c19 = &imux19;
i2c20 = &imux20;
i2c21 = &imux21;
i2c22 = &imux22;
i2c23 = &imux23;
i2c24 = &imux24;
i2c25 = &imux25;
i2c26 = &imux26;
i2c27 = &imux27;
i2c28 = &imux28;
i2c29 = &imux29;
i2c30 = &imux30;
i2c31 = &imux31;
};
chosen {
stdout-path = &uart5;
@@ -25,13 +46,9 @@
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>;
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 7>;
};
};
&fmc {
@@ -124,6 +141,215 @@
&i2c1 {
status = "okay";
//X24 Riser
i2c-switch@71 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
imux16: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
ina230@45 {
compatible = "ti,ina230";
reg = <0x45>;
};
tmp75@48 {
compatible = "ti,tmp75";
reg = <0x48>;
};
tmp421@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
i2c-switch@73 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
imux20: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux21: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux22: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux23: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
imux17: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
ina230@45 {
compatible = "ti,ina230";
reg = <0x45>;
};
tmp421@48 {
compatible = "ti,tmp75";
reg = <0x48>;
};
tmp421@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
i2c-switch@73 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
imux24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux26: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux27: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
imux18: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
ina230@45 {
compatible = "ti,ina230";
reg = <0x45>;
};
tmp421@48 {
compatible = "ti,tmp75";
reg = <0x48>;
};
tmp421@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
i2c-switch@73 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
imux28: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux29: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux30: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux31: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
imux19: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
i2c-switch@40 {
compatible = "ti,ina230";
reg = <0x40>;
};
i2c-switch@41 {
compatible = "ti,ina230";
reg = <0x41>;
};
i2c-switch@45 {
compatible = "ti,ina230";
reg = <0x45>;
};
};
};
};
&i2c2 {
@@ -144,6 +370,42 @@
&i2c5 {
status = "okay";
// CPU Voltage regulators
regulator@48 {
compatible = "infineon,pxe1610";
reg = <0x48>;
};
regulator@4a {
compatible = "infineon,pxe1610";
reg = <0x4a>;
};
regulator@50 {
compatible = "infineon,pxe1610";
reg = <0x50>;
};
regulator@52 {
compatible = "infineon,pxe1610";
reg = <0x52>;
};
regulator@58 {
compatible = "infineon,pxe1610";
reg = <0x58>;
};
regulator@5a {
compatible = "infineon,pxe1610";
reg = <0x5a>;
};
regulator@68 {
compatible = "infineon,pxe1610";
reg = <0x68>;
};
regulator@70 {
compatible = "infineon,pxe1610";
reg = <0x70>;
};
regulator@72 {
compatible = "infineon,pxe1610";
reg = <0x72>;
};
};
&i2c6 {

149
arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts Normal file
View File

@@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
#include "aspeed-g4.dtsi"
/ {
model = "Facebook Wedge 100 BMC";
compatible = "facebook,wedge100-bmc", "aspeed,ast2400";
aliases {
/*
* Override the default uart aliases to avoid breaking
* the legacy applications.
*/
serial0 = &uart5;
serial1 = &uart1;
serial2 = &uart3;
serial3 = &uart4;
};
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS2,9600n8 root=/dev/ram rw";
};
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
};
&wdt1 {
status = "okay";
aspeed,reset-type = "system";
};
&wdt2 {
status = "okay";
aspeed,reset-type = "system";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "fmc0";
#include "facebook-bmc-flash-layout.dtsi"
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
&pinctrl_rxd4_default>;
};
&uart5 {
status = "okay";
};
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
};
};
&i2c8 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&vhub {
status = "okay";
};

141
arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts Normal file
View File

@@ -0,0 +1,141 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
#include "aspeed-g4.dtsi"
/ {
model = "Facebook Wedge 40 BMC";
compatible = "facebook,wedge40-bmc", "aspeed,ast2400";
aliases {
/*
* Override the default uart aliases to avoid breaking
* the legacy applications.
*/
serial0 = &uart5;
serial1 = &uart1;
serial2 = &uart3;
serial3 = &uart4;
};
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS2,9600n8 root=/dev/ram rw";
};
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
};
&wdt1 {
status = "okay";
aspeed,reset-type = "system";
};
&wdt2 {
status = "disabled";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "fmc0";
#include "facebook-bmc-flash-layout.dtsi"
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
&pinctrl_rxd4_default>;
};
&uart5 {
status = "okay";
};
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&vhub {
status = "okay";
};

4
arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
View File

@@ -725,9 +725,9 @@
reg = <0x58>;
};
power-supply@5a {
power-supply@59 {
compatible = "pmbus";
reg = <0x5a>;
reg = <0x59>;
};
};

663
arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts Normal file
View File

@@ -0,0 +1,663 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for Lenovo Hr855xg2 platform
*
* Copyright (C) 2019-present Lenovo
*/
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "HR855XG2 BMC";
compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500";
aliases {
i2c14 = &i2c_riser1;
i2c15 = &i2c_riser2;
i2c16 = &i2c_riser3;
i2c17 = &i2c_M2;
i2c18 = &channel_0;
i2c19 = &channel_1;
i2c20 = &channel_2;
i2c21 = &channel_3;
};
chosen {
stdout-path = &uart5;
bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x00100000>; /* 1M */
};
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
leds {
compatible = "gpio-leds";
heartbeat {
gpios = <&gpio ASPEED_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
fault {
gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>,<&adc 11>,
<&adc 12>,<&adc 13>,<&adc 14>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 15>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi1>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart2 {
/* Rear RS-232 connector */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default
&pinctrl_rxd2_default
&pinctrl_nrts2_default
&pinctrl_ndtr2_default
&pinctrl_ndsr2_default
&pinctrl_ncts2_default
&pinctrl_ndcd2_default
&pinctrl_nri2_default>;
};
&uart3 {
status = "okay";
};
&uart5 {
status = "okay";
};
&ibt {
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&adc{
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default
&pinctrl_adc1_default
&pinctrl_adc2_default
&pinctrl_adc3_default
&pinctrl_adc4_default
&pinctrl_adc5_default
&pinctrl_adc6_default
&pinctrl_adc7_default
&pinctrl_adc8_default
&pinctrl_adc9_default
&pinctrl_adc10_default
&pinctrl_adc11_default
&pinctrl_adc12_default
&pinctrl_adc13_default
&pinctrl_adc14_default
&pinctrl_adc15_default>;
};
&i2c0 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c_riser1: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c_riser2: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c_riser3: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c_M2: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
&i2c1 {
status = "okay";
bus-frequency = <90000>;
HotSwap@10 {
compatible = "adm1272";
reg = <0x10>;
};
VR@45 {
compatible = "pmbus";
reg = <0x45>;
};
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
channel_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
/* temp1 */
tmp75@49 {
compatible = "national,lm75";
reg = <0x49>;
};
/* temp2 */
tmp75@4d {
compatible = "national,lm75";
reg = <0x4d>;
};
eeprom@54 {
compatible = "atmel,24c256";
reg = <0x54>;
pagesize = <16>;
};
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&uhci {
status = "okay";
};
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm2_default
&pinctrl_pwm3_default
&pinctrl_pwm4_default
&pinctrl_pwm5_default
&pinctrl_pwm6_default
&pinctrl_pwm7_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@6 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
fan@8 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x08>;
};
fan@9 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x09>;
};
fan@10 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
};
fan@11 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
};
fan@12 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
};
fan@13 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
};
fan@14 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
};
fan@15 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
};
fan@16 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
};
};
&gpio {
pin_gpio_a1 {
gpio-hog;
gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>;
output-high;
line-name = "BMC_EMMC_RST_N";
};
pin_gpio_a3 {
gpio-hog;
gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
output-high;
line-name = "PCH_PWROK_BMC_FPGA";
};
pin_gpio_b5 {
gpio-hog;
gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "IRQ_BMC_PCH_SMI_LPC_N";
};
pin_gpio_b7 {
gpio-hog;
gpios = <ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>;
output-low;
line-name = "CPU_SM_WP";
};
pin_gpio_e0 {
gpio-hog;
gpios = <ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
input;
line-name = "PDB_PSU_SEL";
};
pin_gpio_e2 {
gpio-hog;
gpios = <ASPEED_GPIO(E, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "LOCATOR_LED_N";
};
pin_gpio_e5 {
gpio-hog;
gpios = <ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "FM_BMC_DBP_PRESENT_R1_N";
};
pin_gpio_e6 {
gpio-hog;
gpios = <ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "BMC_ME_SECURITY_OVERRIDE_N";
};
pin_gpio_f0 {
gpio-hog;
gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "IRQ_BMC_PCH_NMI_R";
};
pin_gpio_f1 {
gpio-hog;
gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
input;
line-name = "CPU2_PROCDIS_BMC_N";
};
pin_gpio_f2 {
gpio-hog;
gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "RM_THROTTLE_EN_N";
};
pin_gpio_f3 {
gpio-hog;
gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "FM_PMBUS_ALERT_B_EN";
};
pin_gpio_f4 {
gpio-hog;
gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "BMC_FORCE_NM_THROTTLE_N";
};
pin_gpio_f6 {
gpio-hog;
gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "FM_BMC_CPU_PWR_DEBUG_N";
};
pin_gpio_g7 {
gpio-hog;
gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "BMC_PCIE_I2C_MUX_RST_N";
};
pin_gpio_h6 {
gpio-hog;
gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "FM_BMC_DBP_PRESENT_R2_N";
};
pin_gpio_i3 {
gpio-hog;
gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "SPI_BMC_BIOS_WP_N";
};
pin_gpio_j1 {
gpio-hog;
gpios = <ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "BMC_USB_SEL";
};
pin_gpio_j2 {
gpio-hog;
gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PDB_SMB_RST_N";
};
pin_gpio_j3 {
gpio-hog;
gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "SPI_BMC_BIOS_HOLD_N";
};
pin_gpio_l0 {
gpio-hog;
gpios = <ASPEED_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PDB_FAN_TACH_SEL";
};
pin_gpio_l1 {
gpio-hog;
gpios = <ASPEED_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "SYS_RESET_BMC_FPGA_N";
};
pin_gpio_l4 {
gpio-hog;
gpios = <ASPEED_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "FM_EFUSE_FAN_G1_EN";
};
pin_gpio_l5 {
gpio-hog;
gpios = <ASPEED_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "FM_EFUSE_FAN_G2_EN";
};
pin_gpio_r6 {
gpio-hog;
gpios = <ASPEED_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
input;
line-name = "CPU3_PROCDIS_BMC_N";
};
pin_gpio_r7 {
gpio-hog;
gpios = <ASPEED_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
input;
line-name = "CPU4_PROCDIS_BMC_N";
};
pin_gpio_s1 {
gpio-hog;
gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "DBP_SYSPWROK_BMC";
};
pin_gpio_s2 {
gpio-hog;
gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCH_RST_RSMRST_N";
};
pin_gpio_s6 {
gpio-hog;
gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "BMC_HW_STRAP_5";
};
pin_gpio_z3 {
gpio-hog;
gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "FM_BMC_PCH_SCI_LPC_N";
};
pin_gpio_aa0 {
gpio-hog;
gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "FW_PSU_ALERT_EN_N";
};
pin_gpio_aa4 {
gpio-hog;
gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "DBP_CPU_PREQ_N";
};
pin_gpio_ab3 {
gpio-hog;
gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "BMC_WDTRST";
};
pin_gpio_ac6 {
gpio-hog;
gpios = <ASPEED_GPIO(AC, 6) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "ESPI_BMC_ALERT_N";
};
};

918
arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts Normal file
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@@ -0,0 +1,918 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/leds/leds-pca955x.h>
/ {
model = "Mihawk BMC";
compatible = "ibm,mihawk-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
flash_memory: region@98000000 {
no-map;
reg = <0x98000000 0x04000000>; /* 64M */
};
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
video_engine_memory: jpegbuffer {
size = <0x02000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
gpio-keys {
compatible = "gpio-keys";
air-water {
label = "air-water";
gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 6)>;
};
checkstop {
label = "checkstop";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
ps0-presence {
label = "ps0-presence";
gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 2)>;
};
ps1-presence {
label = "ps1-presence";
gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 0)>;
};
id-button {
label = "id-button";
gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(F, 1)>;
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
poll-interval = <1000>;
fan0-presence {
label = "fan0-presence";
gpios = <&pca9552 9 GPIO_ACTIVE_LOW>;
linux,code = <9>;
};
fan1-presence {
label = "fan1-presence";
gpios = <&pca9552 10 GPIO_ACTIVE_LOW>;
linux,code = <10>;
};
fan2-presence {
label = "fan2-presence";
gpios = <&pca9552 11 GPIO_ACTIVE_LOW>;
linux,code = <11>;
};
fan3-presence {
label = "fan3-presence";
gpios = <&pca9552 12 GPIO_ACTIVE_LOW>;
linux,code = <12>;
};
fan4-presence {
label = "fan4-presence";
gpios = <&pca9552 13 GPIO_ACTIVE_LOW>;
linux,code = <13>;
};
fan5-presence {
label = "fan5-presence";
gpios = <&pca9552 14 GPIO_ACTIVE_LOW>;
linux,code = <14>;
};
};
leds {
compatible = "gpio-leds";
fault {
retain-state-shutdown;
default-state = "keep";
gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>;
};
power {
retain-state-shutdown;
default-state = "keep";
gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>;
};
rear-id {
retain-state-shutdown;
default-state = "keep";
gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
};
rear-g {
retain-state-shutdown;
default-state = "keep";
gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>;
};
rear-ok {
retain-state-shutdown;
default-state = "keep";
gpios = <&gpio ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
};
fan0 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca9552 0 GPIO_ACTIVE_LOW>;
};
fan1 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca9552 1 GPIO_ACTIVE_LOW>;
};
fan2 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca9552 2 GPIO_ACTIVE_LOW>;
};
fan3 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca9552 3 GPIO_ACTIVE_LOW>;
};
fan4 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca9552 4 GPIO_ACTIVE_LOW>;
};
fan5 {
retain-state-shutdown;
default-state = "keep";
gpios = <&pca9552 5 GPIO_ACTIVE_LOW>;
};
};
fsi: gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
no-gpio-delays;
clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
};
iio-hwmon-12v {
compatible = "iio-hwmon";
io-channels = <&adc 0>;
};
iio-hwmon-5v {
compatible = "iio-hwmon";
io-channels = <&adc 1>;
};
iio-hwmon-3v {
compatible = "iio-hwmon";
io-channels = <&adc 2>;
};
iio-hwmon-vdd0 {
compatible = "iio-hwmon";
io-channels = <&adc 3>;
};
iio-hwmon-vdd1 {
compatible = "iio-hwmon";
io-channels = <&adc 4>;
};
iio-hwmon-vcs0 {
compatible = "iio-hwmon";
io-channels = <&adc 5>;
};
iio-hwmon-vcs1 {
compatible = "iio-hwmon";
io-channels = <&adc 6>;
};
iio-hwmon-vdn0 {
compatible = "iio-hwmon";
io-channels = <&adc 7>;
};
iio-hwmon-vdn1 {
compatible = "iio-hwmon";
io-channels = <&adc 8>;
};
iio-hwmon-vio0 {
compatible = "iio-hwmon";
io-channels = <&adc 9>;
};
iio-hwmon-vio1 {
compatible = "iio-hwmon";
io-channels = <&adc 10>;
};
iio-hwmon-vddra {
compatible = "iio-hwmon";
io-channels = <&adc 11>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 12>;
};
iio-hwmon-vddrb {
compatible = "iio-hwmon";
io-channels = <&adc 13>;
};
iio-hwmon-vddrc {
compatible = "iio-hwmon";
io-channels = <&adc 14>;
};
iio-hwmon-vddrd {
compatible = "iio-hwmon";
io-channels = <&adc 15>;
};
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default
&pinctrl_pwm4_default &pinctrl_pwm5_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@6 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
fan@8 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x08>;
};
fan@9 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x09>;
};
fan@10 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
};
fan@11 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
spi-max-frequency = <50000000>;
partitions {
#address-cells = < 1 >;
#size-cells = < 1 >;
compatible = "fixed-partitions";
u-boot@0 {
reg = < 0 0x60000 >;
label = "u-boot";
};
u-boot-env@60000 {
reg = < 0x60000 0x20000 >;
label = "u-boot-env";
};
obmc-ubi@80000 {
reg = < 0x80000 0x1F80000 >;
label = "obmc-ubi";
};
};
};
flash@1 {
status = "okay";
label = "alt-bmc";
m25p,fast-read;
spi-max-frequency = <50000000>;
partitions {
#address-cells = < 1 >;
#size-cells = < 1 >;
compatible = "fixed-partitions";
u-boot@0 {
reg = < 0 0x60000 >;
label = "alt-u-boot";
};
u-boot-env@60000 {
reg = < 0x60000 0x20000 >;
label = "alt-u-boot-env";
};
obmc-ubi@80000 {
reg = < 0x80000 0x1F80000 >;
label = "alt-obmc-ubi";
};
};
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
label = "pnor";
m25p,fast-read;
spi-max-frequency = <100000000>;
};
};
&lpc_ctrl {
status = "okay";
memory-region = <&flash_memory>;
flash = <&spi1>;
};
&uart1 {
/* Rear RS-232 connector */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_nrts1_default
&pinctrl_ndtr1_default
&pinctrl_ndsr1_default
&pinctrl_ncts1_default
&pinctrl_ndcd1_default
&pinctrl_nri1_default>;
};
&uart2 {
/* APSS */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
};
&uart5 {
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "disabled";
};
&i2c1 {
status = "disabled";
};
&i2c2 {
status = "okay";
/* SAMTEC P0 */
/* SAMTEC P1 */
};
&i2c3 {
status = "okay";
/* APSS */
/* CPLD */
/* PCA9516 (repeater) ->
* CLK Buffer 9FGS9092
* CLK Buffer 9DBL0651BKILFT
* CLK Buffer 9DBL0651BKILFT
* Power Supply 0
* Power Supply 1
* PCA 9552 LED
*/
power-supply@58 {
compatible = "ibm,cffps1";
reg = <0x58>;
};
power-supply@5b {
compatible = "ibm,cffps1";
reg = <0x5b>;
};
pca9552: pca9552@60 {
compatible = "nxp,pca9552";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
};
&i2c4 {
status = "okay";
/* CP0 VDD & VCS : IR35221 */
/* CP0 VDN : IR35221 */
/* CP0 VIO : IR38064 */
/* CP0 VDDR : PXM1330 */
ir35221@70 {
compatible = "infineon,ir35221";
reg = <0x70>;
};
ir35221@72 {
compatible = "infineon,ir35221";
reg = <0x72>;
};
};
&i2c5 {
status = "okay";
/* CP0 VDD & VCS : IR35221 */
/* CP0 VDN : IR35221 */
/* CP0 VIO : IR38064 */
/* CP0 VDDR : PXM1330 */
ir35221@70 {
compatible = "infineon,ir35221";
reg = <0x70>;
};
ir35221@72 {
compatible = "infineon,ir35221";
reg = <0x72>;
};
};
&i2c6 {
status = "okay";
/* pca9548 -> NVMe1 to 8 */
pca9548@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
};
};
&i2c7 {
status = "okay";
/* pca9548 -> NVMe9 to 16 */
pca9548@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
};
};
&i2c8 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
};
&i2c9 {
status = "okay";
/* pca9545 Riser ->
* PCIe x8 Slot3
* PCIe x16 slot4
* PCIe x8 slot5
* I2C BMC RISER PCA9554
* BMC SCL/SDA PCA9554
* PCA9554
*/
/* pca9545 ->
* PCIe x16 Slot1
* PCIe x8 slot2
* PEX8748
*/
pca9545riser@70 {
compatible = "nxp,pca9545";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
interrupt-controller;
#interrupt-cells = <2>;
};
pca9545@71 {
compatible = "nxp,pca9545";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c-mux-idle-disconnect;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&i2c10 {
status = "okay";
/* pca9545 Riser ->
* PCIe x8 Slot8
* PCIe x16 slot9
* PCIe x8 slot10
* I2C BMC RISER PCA9554
* BMC SCL/SDA PCA9554
* PCA9554
*/
/* pca9545 ->
* PCIe x16 Slot1
* PCIe x8 slot2
* PEX8748
*/
pca9545riser@70 {
compatible = "nxp,pca9545";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
interrupt-controller;
#interrupt-cells = <2>;
};
pca9545@71 {
compatible = "nxp,pca9545";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c-mux-idle-disconnect;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&i2c11 {
status = "okay";
/* TPM */
/* RTC RX8900CE */
/* FPGA for power sequence */
/* TMP275A */
/* TMP275A */
/* EMC1462 */
tpm@57 {
compatible = "infineon,slb9645tt";
reg = <0x57>;
};
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};
tmp275@49 {
compatible = "ti,tmp275";
reg = <0x49>;
};
/* chip emc1462 use emc1403 driver */
emc1403@4c {
compatible = "smsc,emc1403";
reg = <0x4c>;
};
};
&i2c12 {
status = "okay";
/* pca9545 ->
* SAS BP1
* SAS BP2
* NVMe BP
* M.2 riser
*/
pca9545@70 {
compatible = "nxp,pca9545";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
interrupt-controller;
#interrupt-cells = <2>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
tmp275@48 {
compatible = "ti,tmp275";
reg = <0x48>;
};
};
};
};
&i2c13 {
status = "okay";
/* pca9548 ->
* NVMe BP
* NVMe HDD17 to 24
*/
pca9548@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
};
};
&vuart {
status = "okay";
};
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
};
&adc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default
&pinctrl_adc1_default
&pinctrl_adc2_default
&pinctrl_adc3_default
&pinctrl_adc4_default
&pinctrl_adc5_default
&pinctrl_adc6_default
&pinctrl_adc7_default
&pinctrl_adc8_default
&pinctrl_adc9_default
&pinctrl_adc10_default
&pinctrl_adc11_default
&pinctrl_adc12_default
&pinctrl_adc13_default
&pinctrl_adc14_default
&pinctrl_adc15_default>;
};
&wdt1 {
aspeed,reset-type = "none";
aspeed,external-signal;
aspeed,ext-push-pull;
aspeed,ext-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdtrst1_default>;
};
&wdt2 {
aspeed,alt-boot;
};
&ibt {
status = "okay";
};
&vhub {
status = "okay";
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
#include "ibm-power9-dual.dtsi"

19
arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
View File

@@ -207,8 +207,8 @@
#size-cells = <0>;
no-gpio-delays;
clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>;
clock-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
data-gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
@@ -494,7 +494,7 @@
};
power-supply@68 {
compatible = "ibm,cffps1";
compatible = "ibm,cffps2";
reg = <0x68>;
};
@@ -504,7 +504,7 @@
};
power-supply@69 {
compatible = "ibm,cffps1";
compatible = "ibm,cffps2";
reg = <0x69>;
};
@@ -963,4 +963,15 @@
status = "okay";
};
&sdmmc {
status = "okay";
};
&sdhci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
};
#include "ibm-power9-dual.dtsi"

10
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
View File

@@ -81,6 +81,12 @@
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "alt";
};
};
&spi {
@@ -222,3 +228,7 @@
&vuart {
status = "okay";
};
&wdt2 {
aspeed,alt-boot;
};

48
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@@ -67,6 +67,26 @@
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@3 {
reg = < 3 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
flash@4 {
reg = < 4 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
};
spi: spi@1e630000 {
@@ -192,6 +212,34 @@
reg = <0x1e720000 0x8000>; // 32K
};
sdmmc: sd-controller@1e740000 {
compatible = "aspeed,ast2400-sd-controller";
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x10000>;
clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
sdhci0: sdhci@100 {
compatible = "aspeed,ast2400-sdhci";
reg = <0x100 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&syscon ASPEED_CLK_SDIO>;
status = "disabled";
};
sdhci1: sdhci@200 {
compatible = "aspeed,ast2400-sdhci";
reg = <0x200 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&syscon ASPEED_CLK_SDIO>;
status = "disabled";
};
};
gpio: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;

35
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@@ -267,13 +267,41 @@
reg = <0x1e720000 0x9000>; // 36K
};
sdmmc: sd-controller@1e740000 {
compatible = "aspeed,ast2500-sd-controller";
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x10000>;
clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
sdhci0: sdhci@100 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x100 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&syscon ASPEED_CLK_SDIO>;
status = "disabled";
};
sdhci1: sdhci@200 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x200 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&syscon ASPEED_CLK_SDIO>;
status = "disabled";
};
};
gpio: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;
compatible = "aspeed,ast2500-gpio";
reg = <0x1e780000 0x1000>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 220>;
gpio-ranges = <&pinctrl 0 0 232>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -1346,6 +1374,11 @@
groups = "SDA2";
};
pinctrl_sgpm_default: sgpm_default {
function = "SGPM";
groups = "SGPM";
};
pinctrl_sgps1_default: sgps1_default {
function = "SGPS1";
groups = "SGPS1";

255
arch/arm/boot/dts/at91-ariag25.dts
View File

@@ -14,11 +14,6 @@
"atmel,at91sam9x5", "atmel,at91sam9";
aliases {
serial0 = &dbgu;
serial1 = &usart0;
serial2 = &usart1;
serial3 = &usart2;
serial4 = &usart3;
serial5 = &uart0;
serial6 = &uart1;
};
@@ -42,132 +37,6 @@
};
};
ahb {
apb {
mmc0: mmc@f0008000 {
/* N.B. Aria has no SD card detect (CD), assumed present */
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
i2c0: i2c@f8010000 {
status = "okay";
};
i2c1: i2c@f8014000 {
status = "okay";
};
/* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */
usart0: serial@f801c000 {
pinctrl-0 = <&pinctrl_usart0
&pinctrl_usart0_rts
&pinctrl_usart0_cts>;
status = "okay";
};
usart1: serial@f8020000 {
pinctrl-0 = <&pinctrl_usart1
/* &pinctrl_usart1_rts */
/* &pinctrl_usart1_cts */
>;
status = "okay";
};
usart2: serial@f8024000 {
/* cannot activate RTS2+CTS2, clash with
* ethernet on PB0 and PB1 */
pinctrl-0 = <&pinctrl_usart2>;
status = "okay";
};
usart3: serial@f8028000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
interrupts = <8 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3
/* &pinctrl_usart3_rts */
/* &pinctrl_usart3_cts */
>;
status = "okay";
};
macb0: ethernet@f802c000 {
phy-mode = "rmii";
/*
* following can be overwritten by bootloader:
* for example u-boot 'ftd set' command
*/
local-mac-address = [00 00 00 00 00 00];
status = "okay";
};
/*
* UART0/1 pins are marked as GPIO on
* Aria documentation.
* Change to "okay" if you need additional serial ports
*/
uart0: serial@f8040000 {
status = "disabled";
};
uart1: serial@f8044000 {
status = "disabled";
};
adc0: adc@f804c000 {
status = "okay";
atmel,adc-channels-used = <0xf>;
};
dbgu: serial@fffff200 {
status = "okay";
};
pinctrl@fffff400 {
w1_0 {
pinctrl_w1_0: w1_0-0 {
atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */
};
};
};
rtc@fffffeb0 {
status = "okay";
};
};
usb0: ohci@600000 {
status = "okay";
num-ports = <3>;
};
usb1: ehci@700000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
@@ -187,3 +56,127 @@
pinctrl-0 = <&pinctrl_w1_0>;
};
};
&adc0 {
status = "okay";
atmel,adc-channels-used = <0xf>;
};
&dbgu {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
/* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */
&macb0 {
phy-mode = "rmii";
/*
* following can be overwritten by bootloader:
* for example u-boot 'ftd set' command
*/
local-mac-address = [00 00 00 00 00 00];
status = "okay";
};
&mmc0 {
/* N.B. Aria has no SD card detect (CD), assumed present */
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
&pinctrl {
w1_0 {
pinctrl_w1_0: w1_0-0 {
atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */
};
};
};
&rtc {
status = "okay";
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
/*
* UART0/1 pins are marked as GPIO on
* Aria documentation.
* Change to "okay" if you need additional serial ports
*/
&uart0 {
status = "disabled";
};
&uart1 {
status = "disabled";
};
&usart0 {
pinctrl-0 = <&pinctrl_usart0
&pinctrl_usart0_rts
&pinctrl_usart0_cts>;
status = "okay";
};
&usart1 {
pinctrl-0 = <&pinctrl_usart1
/* &pinctrl_usart1_rts */
/* &pinctrl_usart1_cts */
>;
status = "okay";
};
&usart2 {
/* cannot activate RTS2+CTS2, clash with
* ethernet on PB0 and PB1 */
pinctrl-0 = <&pinctrl_usart2>;
status = "okay";
};
&usart3 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8028000 0x200>;
interrupts = <8 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3
/* &pinctrl_usart3_rts */
/* &pinctrl_usart3_cts */
>;
status = "okay";
};
&usb0 {
status = "okay";
num-ports = <3>;
};
&usb1 {
status = "okay";
};

100
arch/arm/boot/dts/at91-ariettag25.dts
View File

@@ -6,14 +6,11 @@
*/
/dts-v1/;
#include "at91sam9g25.dtsi"
/ {
model = "Acme Systems Arietta G25";
compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9";
aliases {
serial0 = &dbgu;
};
chosen {
stdout-path = "serial0:115200n8";
};
@@ -32,57 +29,9 @@
};
};
ahb {
apb {
mmc0: mmc@f0008000 {
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
usb2: gadget@f803c000 {
status = "okay";
};
dbgu: serial@fffff200 {
status = "okay";
};
rtc@fffffeb0 {
status = "okay";
};
};
usb0: ohci@600000 {
status = "okay";
num-ports = <3>;
};
usb1: ehci@700000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
arietta_led {
label = "arietta_led";
gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */
@@ -90,3 +39,48 @@
};
};
};
&dbgu {
status = "okay";
};
&mmc0 {
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
&rtc {
status = "okay";
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&usb0 {
num-ports = <3>;
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};

207
arch/arm/boot/dts/at91-cosino.dtsi
View File

@@ -33,122 +33,119 @@
clock-frequency = <12000000>;
};
};
};
ahb {
apb {
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
&adc0 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
&dbgu {
status = "okay";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
nand-controller {
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
uboot@40000 {
label = "u-boot";
reg = <0x40000 0x80000>;
};
};
mmc0: mmc@f0008000 {
pinctrl-0 = <
&pinctrl_board_mmc0
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
ubootenv@c0000 {
label = "U-Boot Env";
reg = <0xc0000 0x140000>;
};
};
dbgu: serial@fffff200 {
status = "okay";
};
usart0: serial@f801c000 {
status = "okay";
};
i2c0: i2c@f8010000 {
status = "okay";
};
adc0: adc@f804c000 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
pinctrl@fffff400 {
mmc0 {
pinctrl_board_mmc0: mmc0-board {
atmel,pins =
<AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
};
watchdog@fffffe40 {
status = "okay";
};
};
ebi: ebi@10000000 {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
nand_controller: nand-controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
uboot@40000 {
label = "u-boot";
reg = <0x40000 0x80000>;
};
ubootenv@c0000 {
label = "U-Boot Env";
reg = <0xc0000 0x140000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
};
};
&i2c0 {
status = "okay";
};
&mmc0 {
pinctrl-0 = <
&pinctrl_board_mmc0
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
};
};
&pinctrl {
mmc0 {
pinctrl_board_mmc0: mmc0-board {
atmel,pins =
<AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
};
};
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&usart0 {
status = "okay";
};
&watchdog {
status = "okay";
};

101
arch/arm/boot/dts/at91-cosino_mega2560.dts
View File

@@ -17,61 +17,58 @@
/ {
model = "HCE Cosino Mega 2560";
compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9";
};
ahb {
apb {
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
&adc0 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
adc0: adc@f804c000 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
&macb0 {
phy-mode = "rmii";
status = "okay";
};
rtc@fffffeb0 {
status = "okay";
};
&mmc1 {
pinctrl-0 = <
&pinctrl_mmc1_slot0_clk_cmd_dat0
&pinctrl_mmc1_slot0_dat1_3>;
status = "okay";
usart1: serial@f8020000 {
status = "okay";
};
usart2: serial@f8024000 {
status = "okay";
};
usb2: gadget@f803c000 {
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};
mmc1: mmc@f000c000 {
pinctrl-0 = <
&pinctrl_mmc1_slot0_clk_cmd_dat0
&pinctrl_mmc1_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
non-removable;
};
};
};
usb0: ohci@600000 {
status = "okay";
num-ports = <3>;
atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */
&pioD 19 GPIO_ACTIVE_LOW
&pioD 20 GPIO_ACTIVE_LOW
>;
};
usb1: ehci@700000 {
status = "okay";
};
slot@0 {
reg = <0>;
bus-width = <4>;
non-removable;
};
};
&rtc {
status = "okay";
};
&usart1 {
status = "okay";
};
&usart2 {
status = "okay";
};
&usb0 {
num-ports = <3>;
atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */
&pioD 19 GPIO_ACTIVE_LOW
&pioD 20 GPIO_ACTIVE_LOW
>;
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};

179
arch/arm/boot/dts/at91-kizboxmini.dts
View File

@@ -32,96 +32,6 @@
};
ahb {
apb {
tcb0: timer@f8008000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
usart0: serial@f801c000 {
status = "okay";
};
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
pwm0: pwm@f8034000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1
&pinctrl_pwm0_pwm1_1>;
status = "okay";
};
dbgu: serial@fffff200 {
status = "okay";
};
watchdog@fffffe40 {
status = "okay";
};
};
usb0: ohci@600000 {
num-ports = <1>;
status = "okay";
};
usb1: ehci@700000 {
status = "okay";
};
ebi: ebi@10000000 {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
nand_controller: nand-controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
@@ -130,7 +40,6 @@
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
};
};
@@ -172,3 +81,91 @@
};
};
};
&dbgu {
status = "okay";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
nand-controller {
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
};
&macb0 {
phy-mode = "rmii";
status = "okay";
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1
&pinctrl_pwm0_pwm1_1>;
status = "okay";
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&usart0 {
status = "okay";
};
&usb0 {
num-ports = <1>;
status = "okay";
};
&usb1 {
status = "okay";
};
&watchdog {
status = "okay";
};

2
arch/arm/boot/dts/at91sam9261ek.dts
View File

@@ -40,7 +40,7 @@
atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
status = "okay";
display0: display {
display0: panel {
bits-per-pixel = <16>;
atmel,lcdcon-backlight;
atmel,dmacon = <0x1>;

2
arch/arm/boot/dts/at91sam9263ek.dts
View File

@@ -110,7 +110,7 @@
display = <&display0>;
status = "okay";
display0: display {
display0: panel {
bits-per-pixel = <16>;
atmel,lcdcon-backlight;
atmel,dmacon = <0x1>;

32
arch/arm/boot/dts/at91sam9g15.dtsi
View File

@@ -11,22 +11,18 @@
/ {
model = "Atmel AT91SAM9G15 SoC";
compatible = "atmel,at91sam9g15", "atmel,at91sam9x5";
ahb {
apb {
pinctrl@fffff400 {
atmel,mux-mask = <
/* A B C */
0xffffffff 0xffe0399f 0x00000000 /* pioA */
0x00040000 0x00047e3f 0x00000000 /* pioB */
0xfdffffff 0x00000000 0xb83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
};
};
&pinctrl {
atmel,mux-mask = <
/* A B C */
0xffffffff 0xffe0399f 0x00000000 /* pioA */
0x00040000 0x00047e3f 0x00000000 /* pioB */
0xfdffffff 0x00000000 0xb83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
};
&pmc {
compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon";
};

12
arch/arm/boot/dts/at91sam9g15ek.dts
View File

@@ -14,14 +14,6 @@
model = "Atmel AT91SAM9G15-EK";
compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
ahb {
apb {
hlcdc: hlcdc@f8038000 {
status = "okay";
};
};
};
backlight: backlight {
status = "okay";
};
@@ -38,3 +30,7 @@
status = "okay";
};
};
&hlcdc {
status = "okay";
};

93
arch/arm/boot/dts/at91sam9g25ek.dts
View File

@@ -12,57 +12,54 @@
/ {
model = "Atmel AT91SAM9G25-EK";
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
};
ahb {
apb {
spi0: spi@f0000000 {
status = "disabled";
};
&i2c0 {
camera@30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "xvclk";
assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
assigned-clock-rates = <25000000>;
status = "okay";
mmc1: mmc@f000c000 {
status = "disabled";
};
i2c0: i2c@f8010000 {
ov2640: camera@30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "xvclk";
assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
assigned-clock-rates = <25000000>;
status = "okay";
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
isi: isi@f8048000 {
status = "okay";
port {
isi_0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
vsync-active = <1>;
hsync-active = <1>;
};
};
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
&isi {
status = "okay";
port {
isi_0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};
&macb0 {
phy-mode = "rmii";
status = "okay";
};
&mmc1 {
status = "disabled";
};
&spi0 {
status = "disabled";
};

22
arch/arm/boot/dts/at91sam9g35ek.dts
View File

@@ -14,19 +14,6 @@
model = "Atmel AT91SAM9G35-EK";
compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
ahb {
apb {
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
hlcdc: hlcdc@f8038000 {
status = "okay";
};
};
};
backlight: backlight {
status = "okay";
};
@@ -43,3 +30,12 @@
status = "okay";
};
};
&hlcdc {
status = "okay";
};
&macb0 {
phy-mode = "rmii";
status = "okay";
};

2
arch/arm/boot/dts/at91sam9m10g45ek.dts
View File

@@ -235,7 +235,7 @@
display = <&display0>;
status = "okay";
display0: display {
display0: panel {
bits-per-pixel = <32>;
atmel,lcdcon-backlight;
atmel,dmacon = <0x1>;

2
arch/arm/boot/dts/at91sam9rlek.dts
View File

@@ -36,7 +36,7 @@
display = <&display0>;
status = "okay";
display0: display {
display0: panel {
bits-per-pixel = <16>;
atmel,lcdcon-backlight;
atmel,dmacon = <0x1>;

44
arch/arm/boot/dts/at91sam9x25ek.dts
View File

@@ -12,28 +12,24 @@
/ {
model = "Atmel AT91SAM9X25-EK";
compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
ahb {
apb {
can1: can@f8004000 {
status = "okay";
};
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
macb1: ethernet@f8030000 {
phy-mode = "rmii";
status = "okay";
};
pwm0: pwm@f8034000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1>;
status = "okay";
};
};
};
};
&can1 {
status = "okay";
};
&macb0 {
phy-mode = "rmii";
status = "okay";
};
&macb1 {
phy-mode = "rmii";
status = "okay";
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1>;
status = "okay";
};

53
arch/arm/boot/dts/at91sam9x35ek.dts
View File

@@ -13,32 +13,29 @@
/ {
model = "Atmel AT91SAM9X35-EK";
compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
ahb {
apb {
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
hlcdc: hlcdc@f8038000 {
status = "okay";
};
};
};
backlight: backlight {
status = "okay";
};
bl_reg: backlight_regulator {
status = "okay";
};
panel: panel {
status = "okay";
};
panel_reg: panel_regulator {
status = "okay";
};
};
&backlight {
status = "okay";
};
&bl_reg {
status = "okay";
};
&hlcdc {
status = "okay";
};
&macb0 {
phy-mode = "rmii";
status = "okay";
};
&panel {
status = "okay";
};
&panel_reg {
status = "okay";
};

2
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@@ -941,7 +941,7 @@
status = "disabled";
};
rtc@fffffeb0 {
rtc: rtc@fffffeb0 {
compatible = "atmel,at91sam9x5-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

206
arch/arm/boot/dts/at91sam9x5_lcd.dtsi
View File

@@ -39,109 +39,109 @@
#pwm-cells = <3>;
};
};
pinctrl@fffff400 {
lcd {
pinctrl_lcd_base: lcd-base-0 {
atmel,pins =
<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
};
pinctrl_lcd_pwm: lcd-pwm-0 {
atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
};
pinctrl_lcd_rgb444: lcd-rgb-0 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
};
pinctrl_lcd_rgb565: lcd-rgb-1 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
};
pinctrl_lcd_rgb666: lcd-rgb-2 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
};
pinctrl_lcd_rgb888: lcd-rgb-3 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
};
};
};
};
};
};
&pinctrl {
lcd {
pinctrl_lcd_base: lcd-base-0 {
atmel,pins =
<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
};
pinctrl_lcd_pwm: lcd-pwm-0 {
atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
};
pinctrl_lcd_rgb444: lcd-rgb-0 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
};
pinctrl_lcd_rgb565: lcd-rgb-1 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
};
pinctrl_lcd_rgb666: lcd-rgb-2 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
};
pinctrl_lcd_rgb888: lcd-rgb-3 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
};
};
};

86
arch/arm/boot/dts/at91sam9x5dm.dtsi
View File

@@ -9,51 +9,6 @@
*/
/ {
ahb {
apb {
i2c0: i2c@f8010000 {
qt1070: keyboard@1b {
compatible = "qt1070";
reg = <0x1b>;
interrupt-parent = <&pioA>;
interrupts = <7 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qt1070_irq>;
wakeup-source;
};
};
hlcdc: hlcdc@f8038000 {
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
port@0 {
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};
adc0: adc@f804c000 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
pinctrl@fffff400 {
board {
pinctrl_qt1070_irq: qt1070_irq {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&hlcdc_pwm 0 50000 0>;
@@ -98,3 +53,44 @@
status = "disabled";
};
};
&adc0 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
&i2c0 {
keyboard@1b {
compatible = "qt1070";
reg = <0x1b>;
interrupt-parent = <&pioA>;
interrupts = <7 0x0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qt1070_irq>;
wakeup-source;
};
};
&hlcdc {
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
port@0 {
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};
&pinctrl {
board {
pinctrl_qt1070_irq: qt1070_irq {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};

265
arch/arm/boot/dts/at91sam9x5ek.dtsi
View File

@@ -16,139 +16,6 @@
stdout-path = "serial0:115200n8";
};
ahb {
apb {
mmc0: mmc@f0008000 {
pinctrl-0 = <
&pinctrl_board_mmc0
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
};
};
mmc1: mmc@f000c000 {
pinctrl-0 = <
&pinctrl_board_mmc1
&pinctrl_mmc1_slot0_clk_cmd_dat0
&pinctrl_mmc1_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
};
};
dbgu: serial@fffff200 {
status = "okay";
};
usart0: serial@f801c000 {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
usb2: gadget@f803c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_board_usb2>;
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};
i2c0: i2c@f8010000 {
status = "okay";
wm8731: wm8731@1a {
compatible = "wm8731";
reg = <0x1a>;
};
};
adc0: adc@f804c000 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
pinctrl@fffff400 {
camera_sensor {
pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 {
atmel,pins =
<AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_MCK */
};
pinctrl_sensor_power: sensor_power-0 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_sensor_reset: sensor_reset-0 {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
mmc0 {
pinctrl_board_mmc0: mmc0-board {
atmel,pins =
<AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
};
};
mmc1 {
pinctrl_board_mmc1: mmc1-board {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */
};
};
usb2 {
pinctrl_board_usb2: usb2-board {
atmel,pins =
<AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB16 gpio vbus sense, deglitch */
};
};
};
spi0: spi@f0000000 {
status = "disabled"; /* conflicts with mmc1 */
cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
m25p80@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
watchdog@fffffe40 {
status = "okay";
};
ssc0: ssc@f0010000 {
status = "okay";
};
};
usb0: ohci@600000 {
status = "okay";
num-ports = <3>;
atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */
&pioD 19 GPIO_ACTIVE_LOW
&pioD 20 GPIO_ACTIVE_LOW
>;
};
usb1: ehci@700000 {
status = "okay";
};
};
sound {
compatible = "atmel,sam9x5-wm8731-audio";
@@ -164,3 +31,135 @@
atmel,audio-codec = <&wm8731>;
};
};
&adc0 {
atmel,adc-ts-wires = <4>;
atmel,adc-ts-pressure-threshold = <10000>;
status = "okay";
};
&dbgu {
status = "okay";
};
&i2c0 {
status = "okay";
wm8731: wm8731@1a {
compatible = "wm8731";
reg = <0x1a>;
};
};
&mmc0 {
pinctrl-0 = <
&pinctrl_board_mmc0
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
};
};
&mmc1 {
pinctrl-0 = <
&pinctrl_board_mmc1
&pinctrl_mmc1_slot0_clk_cmd_dat0
&pinctrl_mmc1_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
};
};
&pinctrl {
camera_sensor {
pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 {
atmel,pins =
<AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_MCK */
};
pinctrl_sensor_power: sensor_power-0 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_sensor_reset: sensor_reset-0 {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
mmc0 {
pinctrl_board_mmc0: mmc0-board {
atmel,pins =
<AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
};
};
mmc1 {
pinctrl_board_mmc1: mmc1-board {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */
};
};
usb2 {
pinctrl_board_usb2: usb2-board {
atmel,pins =
<AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB16 gpio vbus sense, deglitch */
};
};
};
&spi0 {
cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
status = "disabled"; /* conflicts with mmc1 */
m25p80@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&ssc0 {
status = "okay";
};
&usart0 {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&usb0 {
num-ports = <3>;
atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */
&pioD 19 GPIO_ACTIVE_LOW
&pioD 20 GPIO_ACTIVE_LOW
>;
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_board_usb2>;
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&watchdog {
status = "okay";
};

14
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
View File

@@ -8,6 +8,11 @@
compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
model = "Raspberry Pi Model A+";
memory@0 {
device_type = "memory";
reg = <0 0x10000000>;
};
leds {
act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
@@ -99,6 +104,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&pwm {
@@ -107,6 +114,13 @@
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;

14
arch/arm/boot/dts/bcm2835-rpi-a.dts
View File

@@ -8,6 +8,11 @@
compatible = "raspberrypi,model-a", "brcm,bcm2835";
model = "Raspberry Pi Model A";
memory@0 {
device_type = "memory";
reg = <0 0x10000000>;
};
leds {
act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
@@ -94,6 +99,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&pwm {
@@ -102,6 +109,13 @@
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;

14
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
View File

@@ -9,6 +9,11 @@
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
model = "Raspberry Pi Model B+";
memory@0 {
device_type = "memory";
reg = <0 0x20000000>;
};
leds {
act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
@@ -101,6 +106,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&pwm {
@@ -109,6 +116,13 @@
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;

14
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
View File

@@ -9,6 +9,11 @@
compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
model = "Raspberry Pi Model B rev2";
memory@0 {
device_type = "memory";
reg = <0 0x10000000>;
};
leds {
act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
@@ -94,6 +99,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&pwm {
@@ -102,6 +109,13 @@
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;

14
arch/arm/boot/dts/bcm2835-rpi-b.dts
View File

@@ -9,6 +9,11 @@
compatible = "raspberrypi,model-b", "brcm,bcm2835";
model = "Raspberry Pi Model B";
memory@0 {
device_type = "memory";
reg = <0 0x10000000>;
};
leds {
act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
@@ -89,6 +94,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&pwm {
@@ -97,6 +104,13 @@
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;

9
arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts
View File

@@ -79,6 +79,15 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {

5
arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
View File

@@ -10,6 +10,11 @@
};
};
memory@0 {
device_type = "memory";
reg = <0 0x20000000>;
};
reg_3v3: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "3V3";

14
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
View File

@@ -12,6 +12,11 @@
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
model = "Raspberry Pi Zero W";
memory@0 {
device_type = "memory";
reg = <0 0x20000000>;
};
chosen {
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
@@ -100,6 +105,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&sdhci {
@@ -116,6 +123,13 @@
};
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;

14
arch/arm/boot/dts/bcm2835-rpi-zero.dts
View File

@@ -12,6 +12,11 @@
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
model = "Raspberry Pi Zero";
memory@0 {
device_type = "memory";
reg = <0 0x20000000>;
};
leds {
act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
@@ -96,6 +101,15 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {

23
arch/arm/boot/dts/bcm2835-rpi.dtsi
View File

@@ -1,11 +1,6 @@
#include <dt-bindings/power/raspberrypi-power.h>
/ {
memory@0 {
device_type = "memory";
reg = <0 0x10000000>;
};
leds {
compatible = "gpio-leds";
@@ -68,28 +63,10 @@
status = "okay";
};
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio48>;
bus-width = <4>;
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
status = "okay";
bus-width = <4>;
};
&usb {
power-domains = <&power RPI_POWER_DOMAIN_USB>;
};
&hdmi {
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&vec {
power-domains = <&power RPI_POWER_DOMAIN_VEC>;
status = "okay";

10
arch/arm/boot/dts/bcm2836-rpi-2-b.dts
View File

@@ -10,6 +10,7 @@
model = "Raspberry Pi 2 Model B";
memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
};
@@ -105,6 +106,8 @@
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&pwm {
@@ -113,6 +116,13 @@
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;

3
arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
View File

@@ -14,6 +14,7 @@
};
memory@0 {
device_type = "memory";
reg = <0 0x20000000>;
};
@@ -117,6 +118,8 @@
&hdmi {
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&pwm {

3
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
View File

@@ -15,6 +15,7 @@
};
memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
};
@@ -124,6 +125,8 @@
&hdmi {
hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&pwm {

3
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
View File

@@ -15,6 +15,7 @@
};
memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
};
@@ -125,6 +126,8 @@
&hdmi {
hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
/* uart0 communicates with the BT module */

9
arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts
View File

@@ -78,6 +78,15 @@
&hdmi {
hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
status = "okay";
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
bus-width = <4>;
status = "okay";
};
&uart0 {

1
arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
View File

@@ -5,6 +5,7 @@
/ {
memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
};

6
arch/arm/boot/dts/bcm283x.dtsi
View File

@@ -397,7 +397,7 @@
uart0: serial@7e201000 {
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
reg = <0x7e201000 0x1000>;
reg = <0x7e201000 0x200>;
interrupts = <2 25>;
clocks = <&clocks BCM2835_CLOCK_UART>,
<&clocks BCM2835_CLOCK_VPU>;
@@ -428,7 +428,7 @@
spi: spi@7e204000 {
compatible = "brcm,bcm2835-spi";
reg = <0x7e204000 0x1000>;
reg = <0x7e204000 0x200>;
interrupts = <2 22>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
dmas = <&dma 6>, <&dma 7>;
@@ -440,7 +440,7 @@
i2c0: i2c@7e205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
reg = <0x7e205000 0x200>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;

2
arch/arm/boot/dts/da850-evm.dts
View File

@@ -281,7 +281,7 @@
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
compatible = "jedec,spi-nor";
spi-max-frequency = <30000000>;
m25p,fast-read;
reg = <0>;

2
arch/arm/boot/dts/ep7211-edb7211.dts
View File

@@ -25,11 +25,11 @@
display: display {
model = "320x240x4";
native-mode = <&timing0>;
bits-per-pixel = <4>;
ac-prescale = <17>;
display-timings {
native-mode = <&timing0>;
timing0: 320x240 {
hactive = <320>;
hback-porch = <0>;

3
arch/arm/boot/dts/exynos3250.dtsi
View File

@@ -450,8 +450,7 @@
};
adc: adc@126c0000 {
compatible = "samsung,exynos3250-adc",
"samsung,exynos-adc-v2";
compatible = "samsung,exynos3250-adc";
reg = <0x126C0000 0x100>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc", "sclk";

18
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
View File

@@ -377,7 +377,7 @@
buck1_reg: BUCK1 {
regulator-name = "vdd_mif";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -386,7 +386,7 @@
buck2_reg: BUCK2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1456250>;
regulator-max-microvolt = <1456250>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -395,7 +395,7 @@
buck3_reg: BUCK3 {
regulator-name = "vdd_int";
regulator-min-microvolt = <875000>;
regulator-max-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -404,7 +404,7 @@
buck4_reg: BUCK4 {
regulator-name = "vdd_g3d";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -413,7 +413,7 @@
buck5_reg: BUCK5 {
regulator-name = "vdd_m12";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -422,7 +422,7 @@
buck6_reg: BUCK6 {
regulator-name = "vdd12_5m";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
@@ -431,7 +431,7 @@
buck7_reg: BUCK7 {
regulator-name = "pvdd_buck7";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-boot-on;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
@@ -440,7 +440,7 @@
buck8_reg: BUCK8 {
regulator-name = "pvdd_buck8";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
@@ -449,7 +449,7 @@
buck9_reg: BUCK9 {
regulator-name = "vddf28_emmc";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
op_mode = <1>; /* Normal Mode */
};
};

9
arch/arm/boot/dts/exynos5250-arndale.dts
View File

@@ -461,8 +461,8 @@
buck4_reg: BUCK4 {
regulator-name = "vdd_g3d";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
@@ -543,6 +543,11 @@
status = "okay";
};
&mali {
mali-supply = <&buck4_reg>;
status = "okay";
};
&mixer {
status = "okay";
};

5
arch/arm/boot/dts/exynos5250-snow-common.dtsi
View File

@@ -529,6 +529,11 @@
status = "okay";
};
&mali {
mali-supply = <&buck4_reg>;
status = "okay";
};
&mixer {
status = "okay";
};

48
arch/arm/boot/dts/exynos5250.dtsi
View File

@@ -328,6 +328,53 @@
iommus = <&sysmmu_rotator>;
};
mali: gpu@11800000 {
compatible = "samsung,exynos5250-mali", "arm,mali-t604";
reg = <0x11800000 0x5000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&clock CLK_G3D>;
clock-names = "core";
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&pd_g3d>;
status = "disabled";
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <925000>;
};
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
opp-microvolt = <925000>;
};
opp-266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <1025000>;
};
opp-350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <1075000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1125000>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <1150000>;
};
opp-533000000 {
opp-hz = /bits/ 64 <533000000>;
opp-microvolt = <1250000>;
};
};
};
tmu: tmu@10060000 {
compatible = "samsung,exynos5250-tmu";
reg = <0x10060000 0x100>;
@@ -346,6 +393,7 @@
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
status = "disabled";
};

1
arch/arm/boot/dts/exynos5420-peach-pit.dts
View File

@@ -440,6 +440,7 @@
regulator-name = "vdd_ldo10";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};

13
arch/arm/boot/dts/exynos5420.dtsi
View File

@@ -294,11 +294,11 @@
label = "MFC";
};
msc_pd: power-domain@10044120 {
g3d_pd: power-domain@10044080 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044120 0x20>;
reg = <0x10044080 0x20>;
#power-domain-cells = <0>;
label = "MSC";
label = "G3D";
};
disp_pd: power-domain@100440c0 {
@@ -315,6 +315,13 @@
label = "MAU";
};
msc_pd: power-domain@10044120 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044120 0x20>;
#power-domain-cells = <0>;
label = "MSC";
};
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;

1
arch/arm/boot/dts/exynos5800-peach-pi.dts
View File

@@ -440,6 +440,7 @@
regulator-name = "vdd_ldo10";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};

9
arch/arm/boot/dts/exynos5800.dtsi
View File

@@ -131,3 +131,12 @@
&mfc {
compatible = "samsung,mfc-v8";
};
&soc {
cam_pd: power-domain@10045100 {
compatible = "samsung,exynos4210-pd";
reg = <0x10045100 0x20>;
#power-domain-cells = <0>;
label = "CAM";
};
};

37
arch/arm/boot/dts/gemini-nas4220b.dts
View File

@@ -20,7 +20,7 @@
};
chosen {
bootargs = "console=ttyS0,19200n8";
bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait";
stdout-path = &uart0;
};
@@ -81,37 +81,10 @@
/* 16MB of flash */
reg = <0x30000000 0x01000000>;
partition@0 {
label = "RedBoot";
reg = <0x00000000 0x00020000>;
read-only;
};
partition@20000 {
label = "Kernel";
reg = <0x00020000 0x00300000>;
};
partition@320000 {
label = "Ramdisk";
reg = <0x00320000 0x00600000>;
};
partition@920000 {
label = "Application";
reg = <0x00920000 0x00600000>;
};
partition@f20000 {
label = "VCTL";
reg = <0x00f20000 0x00020000>;
read-only;
};
partition@f40000 {
label = "CurConf";
reg = <0x00f40000 0x000a0000>;
read-only;
};
partition@fe0000 {
label = "FIS directory";
reg = <0x00fe0000 0x00020000>;
read-only;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0xfe0000 */
fis-index-block = <0x1fc>;
};
};

56
arch/arm/boot/dts/gemini-sl93512r.dts
View File

@@ -24,7 +24,7 @@
};
chosen {
bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait";
bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait";
stdout-path = &uart0;
};
@@ -36,8 +36,8 @@
wakeup-source;
linux,code = <KEY_WPS_BUTTON>;
label = "WPS";
/* Conflict with NAND flash */
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
/* Conflicts with TVC and extended flash */
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
};
button-setup {
@@ -143,54 +143,30 @@
/* 16MB of flash */
reg = <0x30000000 0x01000000>;
partition@0 {
label = "BOOT";
reg = <0x00000000 0x00020000>;
read-only;
};
partition@120000 {
label = "Kern";
reg = <0x00020000 0x00300000>;
};
partition@320000 {
label = "Ramdisk";
reg = <0x00320000 0x00600000>;
};
partition@920000 {
label = "Application";
reg = <0x00920000 0x00600000>;
};
partition@f20000 {
label = "VCTL";
reg = <0x00f20000 0x00020000>;
read-only;
};
partition@f40000 {
label = "CurConf";
reg = <0x00f40000 0x000a0000>;
read-only;
};
partition@fe0000 {
label = "FIS directory";
reg = <0x00fe0000 0x00020000>;
read-only;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0xfe0000 */
fis-index-block = <0x1fc>;
};
};
syscon: syscon@40000000 {
pinctrl {
/*
* gpio0egrp cover line 16 used by HD LED
* gpio0fgrp cover line 17, 18 used by wireless LED and reset button
* gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY
* gpio0kgrp cover line 31 used by USB LED
* gpio0agrp cover line 0, used by WPS button
* gpio0fgrp cover line 16 used by HD LED
* gpio0ggrp cover line 17, 18 used by wireless LAN LED and
* reset button OR USB ID select on 17 and USB VBUS select
* on 18. (Confusing.)
* gpio0igrp cover line 21, 22 used by MDIO for Marvell PHY
*/
gpio0_default_pins: pinctrl-gpio0 {
mux {
function = "gpio0";
groups = "gpio0egrp",
groups = "gpio0agrp",
"gpio0fgrp",
"gpio0hgrp";
"gpio0ggrp",
"gpio0igrp";
};
};
/*

2
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
View File

@@ -14,8 +14,8 @@
bits-per-pixel = <16>;
fsl,pcr = <0xcad08b80>;
bus-width = <18>;
native-mode = <&qvga_timings>;
display-timings {
native-mode = <&qvga_timings>;
qvga_timings: 320x240 {
clock-frequency = <6500000>;
hactive = <320>;

2
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts
View File

@@ -14,8 +14,8 @@
bits-per-pixel = <16>;
fsl,pcr = <0xfa208b80>;
bus-width = <18>;
native-mode = <&dvi_svga_timings>;
display-timings {
native-mode = <&dvi_svga_timings>;
dvi_svga_timings: 800x600 {
clock-frequency = <40000000>;
hactive = <800>;

2
arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts
View File

@@ -14,8 +14,8 @@
bits-per-pixel = <16>;
fsl,pcr = <0xfa208b80>;
bus-width = <18>;
native-mode = <&dvi_vga_timings>;
display-timings {
native-mode = <&dvi_vga_timings>;
dvi_vga_timings: 640x480 {
clock-frequency = <31250000>;
hactive = <640>;

2
arch/arm/boot/dts/imx25-pdk.dts
View File

@@ -76,8 +76,8 @@
bits-per-pixel = <16>;
fsl,pcr = <0xfa208b80>;
bus-width = <18>;
native-mode = <&wvga_timings>;
display-timings {
native-mode = <&wvga_timings>;
wvga_timings: 640x480 {
hactive = <640>;
vactive = <480>;

2
arch/arm/boot/dts/imx27-apf27dev.dts
View File

@@ -12,10 +12,10 @@
display: display {
model = "Chimei-LW700AT9003";
native-mode = <&timing0>;
bits-per-pixel = <16>; /* non-standard but required */
fsl,pcr = <0xfae80083>; /* non-standard but required */
display-timings {
native-mode = <&timing0>;
timing0: 800x480 {
clock-frequency = <33000033>;
hactive = <800>;

2
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
View File

@@ -11,11 +11,11 @@
display0: CMO-QVGA {
model = "CMO-QVGA";
native-mode = <&timing0>;
bits-per-pixel = <16>;
fsl,pcr = <0xfad08b80>;
display-timings {
native-mode = <&timing0>;
timing0: 320x240 {
clock-frequency = <6500000>;
hactive = <320>;

2
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
View File

@@ -15,10 +15,10 @@
display: display {
model = "Primeview-PD050VL1";
native-mode = <&timing0>;
bits-per-pixel = <16>; /* non-standard but required */
fsl,pcr = <0xf0c88080>; /* non-standard but required */
display-timings {
native-mode = <&timing0>;
timing0: 640x480 {
hactive = <640>;
vactive = <480>;

2
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
View File

@@ -14,11 +14,11 @@
display0: LQ035Q7 {
model = "Sharp-LQ035Q7";
native-mode = <&timing0>;
bits-per-pixel = <16>;
fsl,pcr = <0xf00080c0>;
display-timings {
native-mode = <&timing0>;
timing0: 240x320 {
clock-frequency = <5500000>;
hactive = <240>;

3
arch/arm/boot/dts/imx53-m53menlo.dts
View File

@@ -54,7 +54,8 @@
};
panel {
compatible = "edt,etm070080dh6";
compatible = "edt,etm0700g0dh6";
pinctrl-0 = <&pinctrl_display_gpio>;
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
port {

11
arch/arm/boot/dts/imx6qdl-colibri.dtsi
View File

@@ -140,7 +140,18 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
reg = <0>;
micrel,led-mode = <0>;
};
};
};
&hdmi {

2
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
View File

@@ -556,8 +556,6 @@
non-removable;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_wlan_vmmc>;
vqmmc-1-8-v;
ocr-limit = <0x180>; /* 1.65v - 2.1v */
cap-power-off-card;
keep-power-in-suspend;
status = "okay";

2
arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
View File

@@ -128,7 +128,7 @@
};
rtc@51 {
compatible = "nxp,rtc8564";
compatible = "epson,rtc8564";
reg = <0x51>;
};

73
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View File

@@ -33,6 +33,30 @@
spdif-out;
};
reg_1p5v: regulator-1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_2p8v: regulator-2p8v {
compatible = "regulator-fixed";
regulator-name = "2P8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
@@ -94,6 +118,29 @@
VDDIO-supply = <&reg_3p3v>;
lrclk-strength = <3>;
};
camera@3c {
compatible = "ovti,ov5645";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5645>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO2>;
clock-names = "xclk";
clock-frequency = <24000000>;
vdddo-supply = <&reg_1p8v>;
vdda-supply = <&reg_2p8v>;
vddd-supply = <&reg_1p5v>;
enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
port {
ov5645_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&iomuxc {
@@ -128,7 +175,6 @@
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@@ -152,6 +198,14 @@
>;
};
pinctrl_ov5645: ov5645grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
@@ -226,12 +280,23 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5645_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;

4
arch/arm/boot/dts/imx6qdl.dtsi
View File

@@ -171,8 +171,6 @@
gpmi: gpmi-nand@112000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -695,7 +693,7 @@
};
anatop: anatop@20c8000 {
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,

18
arch/arm/boot/dts/imx6sl.dtsi
View File

@@ -77,15 +77,6 @@
};
};
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
ckil {
compatible = "fixed-clock";
@@ -133,6 +124,15 @@
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;

24
arch/arm/boot/dts/imx6sll.dtsi
View File

@@ -75,15 +75,6 @@
};
};
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
ckil: clock-ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -134,6 +125,15 @@
reg = <0x00900000 0x20000>;
};
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
@@ -234,7 +234,7 @@
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
"fsl,imx21-uart";
reg = <0x02018000 0x4000>;
interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
@@ -621,7 +621,7 @@
};
sdma: dma-controller@20ec000 {
compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_IPG>,
@@ -801,7 +801,7 @@
compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
"fsl,imx21-uart";
reg = <0x021f4000 0x4000>;
interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SLL_CLK_UART5_IPG>,

22
arch/arm/boot/dts/imx6sx.dtsi
View File

@@ -90,15 +90,6 @@
};
};
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
ckil: clock-ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -181,6 +172,15 @@
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
intc: interrupt-controller@a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
@@ -926,8 +926,8 @@
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";
};

102
arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts Normal file
View File

@@ -0,0 +1,102 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx6ul-kontron-n6310-s.dts"
/ {
model = "Kontron N6310 S 43";
compatible = "kontron,imx6ul-n6310-s-43", "kontron,imx6ul-n6310-s",
"kontron,imx6ul-n6310-som", "fsl,imx6ul";
backlight {
compatible = "pwm-backlight";
pwms = <&pwm7 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
};
&i2c4 {
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cap_touch>;
interrupt-parent = <&gpio5>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
/* Leave status disabled because of missing display panel node */
};
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
status = "okay";
};
&iomuxc {
pinctrl_cap_touch: captouchgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
>;
};
};

420
arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts Normal file
View File

@@ -0,0 +1,420 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include "imx6ul-kontron-n6310-som.dtsi"
/ {
model = "Kontron N6310 S";
compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som",
"fsl,imx6ul";
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "debug-led1";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
led2 {
label = "debug-led2";
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "debug-led3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm8 0 5000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref-adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
eeprom@0 {
compatible = "anvo,anv32e61w", "atmel,at25";
reg = <0>;
spi-max-frequency = <20000000>;
spi-cpha;
spi-cpol;
pagesize = <1>;
size = <8192>;
address-width = <16>;
};
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
>;
};
/* FRAM */
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
>;
};
pinctrl_enet2_mdio: enet2mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
/*
* mux unused RTS to make sure it doesn't cause
* any interrupts when it is undefined
*/
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
>;
};
};

134
arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi Normal file
View File

@@ -0,0 +1,134 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx6ul.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Kontron N6310 SOM";
compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul";
memory@80000000 {
reg = <0x80000000 0x10000000>;
device_type = "memory";
};
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
spi-flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
phy-mode = "rmii";
status = "disabled";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <108000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
partition@0 {
label = "ubi1";
reg = <0x00000000 0x08000000>;
};
partition@8000000 {
label = "ubi2";
reg = <0x08000000 0x08000000>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_out>;
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
>;
};
pinctrl_enet1_mdio: enet1mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
};
pinctrl_reset_out: rstoutgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
};

37
arch/arm/boot/dts/imx6ul-opos6uldev.dts
View File

@@ -56,7 +56,7 @@
stdout-path = &uart1;
};
backlight {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 191000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -97,6 +97,18 @@
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
};
panel: panel {
compatible = "armadeus,st0700-adapt";
power-supply = <&reg_3v3>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&lcdif_out>;
};
};
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
@@ -182,28 +194,11 @@
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
display = <&display0>;
lcd-supply = <&reg_3v3>;
status = "okay";
display0: display0 {
bits-per-pixel = <32>;
bus-width = <18>;
display-timings {
timing0: timing0 {
clock-frequency = <33000033>;
hactive = <800>;
vactive = <480>;
hback-porch = <96>;
hfront-porch = <96>;
vback-porch = <20>;
vfront-porch = <21>;
hsync-len = <64>;
vsync-len = <4>;
de-active = <1>;
pixelclk-active = <0>;
};
port {
lcdif_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};

53
arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi → arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
View File

@@ -7,10 +7,9 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx6ul.dtsi"
/ {
model = "Phytec phyCORE i.MX6 UltraLite";
model = "PHYTEC phyCORE-i.MX6 UltraLite";
compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
chosen {
@@ -31,8 +30,7 @@
pinctrl-0 = <&pinctrl_gpioleds_som>;
compatible = "gpio-leds";
led_green {
label = "phycore:green";
phycore-green {
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
@@ -43,20 +41,21 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
phy-handle = <&ethphy1>;
status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
ethphy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
status = "disabled";
};
};
};
@@ -65,12 +64,12 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
status = "disabled";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 =<&pinctrl_i2c1>;
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
@@ -90,19 +89,28 @@
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
no-1-8-v;
non-removable;
status = "disabled";
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
>;
};
@@ -145,4 +153,19 @@
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};

42
arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts → arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
View File

@@ -5,13 +5,15 @@
*/
/dts-v1/;
#include "imx6ul-phytec-pcl063.dtsi"
#include "imx6ul-phytec-phyboard-segin.dtsi"
#include "imx6ul-phytec-peb-eval-01.dtsi"
#include "imx6ul.dtsi"
#include "imx6ul-phytec-phycore-som.dtsi"
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
/ {
model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
"phytec,imx6ul-pcl063", "fsl,imx6ul";
};
&adc1 {
@@ -27,9 +29,18 @@
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&ethphy1 {
status = "okay";
};
&ethphy2 {
status = "okay";
};
&fec1 {
status = "okay";
};
@@ -37,6 +48,10 @@
status = "okay";
};
&gpmi {
status = "okay";
};
&i2c_rtc {
status = "okay";
};
@@ -76,14 +91,3 @@
&usdhc1 {
status = "okay";
};
&iomuxc {
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
>;
};
};

16
arch/arm/boot/dts/imx6ul-phytec-peb-eval-01.dtsi → arch/arm/boot/dts/imx6ul-phytec-segin-peb-eval-01.dtsi
View File

@@ -21,20 +21,22 @@
};
};
user_leds: leds {
user_leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_user_leds>;
status = "disabled";
led_yellow {
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
user-led1 {
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
led_red {
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
user-led2 {
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "gpio";
default-state = "on";
};
};
};

31
arch/arm/boot/dts/imx6ul-phytec-phyboard-segin.dtsi → arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
View File

@@ -5,7 +5,7 @@
*/
/ {
model = "Phytec phyBOARD-Segin i.MX6 UltraLite";
model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
aliases {
@@ -103,11 +103,18 @@
assigned-clock-rates = <786432000>;
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
phy-handle = <&ethphy2>;
status = "disabled";
};
@@ -160,11 +167,12 @@
};
&mdio {
ethphy1: ethernet-phy@2 {
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
status = "disabled";
};
};
@@ -224,16 +232,25 @@
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
>;
};

53
arch/arm/boot/dts/imx6ul.dtsi
View File

@@ -93,18 +93,6 @@
};
};
intc: interrupt-controller@a01000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
reg = <0x00a01000 0x1000>,
<0x00a02000 0x2000>,
<0x00a04000 0x2000>,
<0x00a06000 0x2000>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
@@ -171,6 +159,18 @@
reg = <0x00900000 0x20000>;
};
intc: interrupt-controller@a01000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
reg = <0x00a01000 0x1000>,
<0x00a02000 0x2000>,
<0x00a04000 0x2000>,
<0x00a06000 0x2000>;
};
dma_apbh: dma-apbh@1804000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x01804000 0x2000>;
@@ -227,6 +227,8 @@
clocks = <&clks IMX6UL_CLK_ECSPI1>,
<&clks IMX6UL_CLK_ECSPI1>;
clock-names = "ipg", "per";
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -239,6 +241,8 @@
clocks = <&clks IMX6UL_CLK_ECSPI2>,
<&clks IMX6UL_CLK_ECSPI2>;
clock-names = "ipg", "per";
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -251,6 +255,8 @@
clocks = <&clks IMX6UL_CLK_ECSPI3>,
<&clks IMX6UL_CLK_ECSPI3>;
clock-names = "ipg", "per";
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -263,6 +269,8 @@
clocks = <&clks IMX6UL_CLK_ECSPI4>,
<&clks IMX6UL_CLK_ECSPI4>;
clock-names = "ipg", "per";
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -510,8 +518,8 @@
<&clks IMX6UL_CLK_ENET2_REF_125M>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<1>;
fsl,num-rx-queues=<1>;
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
status = "disabled";
};
@@ -845,8 +853,8 @@
<&clks IMX6UL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<1>;
fsl,num-rx-queues=<1>;
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
status = "disabled";
};
@@ -858,7 +866,7 @@
<&clks IMX6UL_CLK_USDHC1>,
<&clks IMX6UL_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
bus-width = <4>;
status = "disabled";
@@ -873,7 +881,7 @@
<&clks IMX6UL_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled";
};
@@ -957,6 +965,15 @@
};
};
csi: csi@21c4000 {
compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
reg = <0x021c4000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CSI>;
clock-names = "mclk";
status = "disabled";
};
lcdif: lcdif@21c8000 {
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
reg = <0x021c8000 0x4000>;

24
arch/arm/boot/dts/imx6ull-phytec-phycore-som.dtsi Normal file
View File

@@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
#include "imx6ul-phytec-phycore-som.dtsi"
/ {
model = "PHYTEC phyCORE-i.MX6 ULL";
compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull";
};
&iomuxc {
/delete-node/ gpioledssomgrp;
};
&iomuxc_snvs {
pinctrl_gpioleds_som: gpioledssomgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
>;
};
};

93
arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts Normal file
View File

@@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";
compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10",
"phytec,imx6ull-pcl063","fsl,imx6ull";
};
&adc1 {
status = "okay";
};
&can1 {
status = "okay";
};
&tlv320 {
status = "okay";
};
&ecspi3 {
status = "okay";
};
&ethphy1 {
status = "okay";
};
&ethphy2 {
status = "okay";
};
&fec1 {
status = "okay";
};
&fec2 {
status = "okay";
};
&i2c_rtc {
status = "okay";
};
&reg_can1_en {
status = "okay";
};
&reg_sound_1v8 {
status = "okay";
};
&reg_sound_3v3 {
status = "okay";
};
&sai2 {
status = "okay";
};
&sound {
status = "okay";
};
&uart5 {
status = "okay";
};
&usbotg1 {
status = "okay";
};
&usbotg2 {
status = "okay";
};
&usdhc1 {
status = "okay";
};
&usdhc2 {
status = "okay";
};

93
arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts Normal file
View File

@@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
"phytec,imx6ull-pcl063", "fsl,imx6ull";
};
&adc1 {
status = "okay";
};
&can1 {
status = "okay";
};
&tlv320 {
status = "okay";
};
&ecspi3 {
status = "okay";
};
&ethphy1 {
status = "okay";
};
&ethphy2 {
status = "okay";
};
&fec1 {
status = "okay";
};
&fec2 {
status = "okay";
};
&gpmi {
status = "okay";
};
&i2c_rtc {
status = "okay";
};
&reg_can1_en {
status = "okay";
};
&reg_sound_1v8 {
status = "okay";
};
&reg_sound_3v3 {
status = "okay";
};
&sai2 {
status = "okay";
};
&sound {
status = "okay";
};
&uart5 {
status = "okay";
};
&usbotg1 {
status = "okay";
};
&usbotg2 {
status = "okay";
};
&usdhc1 {
status = "okay";
};

45
arch/arm/boot/dts/imx6ull-phytec-segin-lc-rdk-nand.dts Normal file
View File

@@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
"phytec,imx6ull-pcl063", "fsl,imx6ull";
};
&adc1 {
status = "okay";
};
&ethphy1 {
status = "okay";
};
&fec1 {
status = "okay";
};
&gpmi {
status = "okay";
};
&i2c_rtc {
status = "okay";
};
&usbotg1 {
status = "okay";
};
&usdhc1 {
status = "okay";
};

19
arch/arm/boot/dts/imx6ull-phytec-segin-peb-eval-01.dtsi Normal file
View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
&iomuxc {
/delete-node/ gpio_keysgrp;
};
&iomuxc_snvs {
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x79
>;
};
};

38
arch/arm/boot/dts/imx6ull-phytec-segin.dtsi Normal file
View File

@@ -0,0 +1,38 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
#include "imx6ul-phytec-segin.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
};
&iomuxc {
/delete-node/ flexcan1engrp;
/delete-node/ rtcintgrp;
/delete-node/ stmpegrp;
};
&iomuxc_snvs {
princtrl_flexcan1_en: flexcan1engrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
>;
};
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
>;
};
pinctrl_stmpe: stmpegrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
>;
};
};

86
arch/arm/boot/dts/imx7-colibri.dtsi
View File

@@ -54,6 +54,7 @@
regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_module_3v3_avdd: regulator-module-3v3-avdd {
@@ -61,6 +62,7 @@
regulator-name = "+V3.3_AVDD_AUDIO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound {
@@ -99,8 +101,9 @@
};
&fec1 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet1>;
pinctrl-1 = <&pinctrl_enet1_sleep>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
@@ -115,6 +118,18 @@
fsl,magic-packet;
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "disabled";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "disabled";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -125,8 +140,12 @@
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
codec: sgtl5000@a {
@@ -227,8 +246,11 @@
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_recovery>;
scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&lcdif {
@@ -267,10 +289,6 @@
status = "okay";
};
&snvs_pwrkey {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
@@ -323,16 +341,16 @@
vmmc-supply = <&reg_module_3v3>;
vqmmc-supply = <&reg_DCDC3>;
non-removable;
sdhci-caps-mask = <0x80000000 0x0>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
&pinctrl_gpio7>;
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 63 */
MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
@@ -413,6 +431,13 @@
>;
};
pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
>;
};
pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
fsl,pins = <
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
@@ -442,6 +467,22 @@
>;
};
pinctrl_enet1_sleep: enet1sleepgrp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
>;
};
pinctrl_ecspi3_cs: ecspi3-cs-grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
@@ -456,10 +497,17 @@
>;
};
pinctrl_flexcan1: flexcan1-grp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
>;
};
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
>;
};
@@ -495,6 +543,13 @@
>;
};
pinctrl_i2c4_recovery: i2c4-recoverygrp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
>;
};
pinctrl_lcdif_dat: lcdif-dat-grp {
fsl,pins = <
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
@@ -695,6 +750,13 @@
>;
};
pinctrl_i2c1_recovery: i2c1-recoverygrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
>;
};
pinctrl_cd_usdhc1: usdhc1-cd-grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */

6
arch/arm/boot/dts/imx7d-cl-som-imx7.dts
View File

@@ -44,7 +44,7 @@
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
@@ -54,10 +54,12 @@
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
@@ -70,7 +72,7 @@
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";

357
arch/arm/boot/dts/imx7d-zii-rmu2.dts Normal file
View File

@@ -0,0 +1,357 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device tree file for ZII's RMU2 board
*
* RMU - Remote Modem Unit
*
* Copyright (C) 2019 Zodiac Inflight Innovations
*/
/dts-v1/;
#include <dt-bindings/thermal/thermal.h>
#include "imx7d.dtsi"
/ {
model = "ZII RMU2 Board";
compatible = "zii,imx7d-rmu2", "fsl,imx7d";
chosen {
stdout-path = &uart2;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&pinctrl_leds_debug>;
pinctrl-names = "default";
debug {
label = "zii:green:debug1";
gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&cpu0 {
arm-supply = <&sw1a_reg>;
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-handle = <&fec1_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
fec1_phy: ethernet-phy@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1_phy_reset>,
<&pinctrl_enet1_phy_interrupt>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
};
eeprom@52 {
compatible = "atmel,24c04";
reg = <0x52>;
};
};
&snvs_rtc {
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
rave-sp {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
watchdog {
compatible = "zii,rave-sp-watchdog";
};
eeprom@a3 {
compatible = "zii,rave-sp-eeprom";
reg = <0xa3 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
zii,eeprom-name = "main-eeprom";
};
};
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
no-1-8-v;
no-sdio;
keep-power-in-suspend;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
no-1-8-v;
non-removable;
no-sdio;
no-sd;
keep-power-in-suspend;
status = "okay";
};
&wdog1 {
status = "disabled";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
MX7D_PAD_SD2_WP__ENET1_MDC 0x3
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
>;
};
pinctrl_enet1_phy_reset: enet1phyresetgrp {
fsl,pins = <
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
pinctrl_leds_debug: ledsgrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
>;
};
};
&iomuxc_lpsr {
pinctrl_enet1_phy_interrupt: enet1phyinterruptgrp {
fsl,phy = <
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08
>;
};
};

4
arch/arm/boot/dts/imx7d-zii-rpu2.dts
View File

@@ -669,10 +669,6 @@
status = "disabled";
};
&snvs_pwrkey {
status = "disabled";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <

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