Merge tag 'dmaengine-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul: "Core: - Support out of order dma completion - Support for repeating transaction New controllers: - Support for Actions S700 DMA engine - Renesas R8A774E1, r8a7742 controller binding - New driver for Xilinx DPDMA controller Other: - Support of out of order dma completion in idxd driver - W=1 warning cleanup of subsystem - Updates to ti-k3-dma, dw, idxd drivers" * tag 'dmaengine-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (68 commits) dmaengine: dw: Don't include unneeded header to platform data header dmaengine: Actions: Add support for S700 DMA engine dmaengine: Actions: get rid of bit fields from dma descriptor dt-bindings: dmaengine: convert Actions Semi Owl SoCs bindings to yaml dmaengine: idxd: add missing invalid flags field to completion dmaengine: dw: Initialize max_sg_burst capability dmaengine: dw: Introduce max burst length hw config dmaengine: dw: Initialize min and max burst DMA device capability dmaengine: dw: Set DMA device max segment size parameter dmaengine: dw: Take HC_LLP flag into account for noLLP auto-config dmaengine: Introduce DMA-device device_caps callback dmaengine: Introduce max SG burst capability dmaengine: Introduce min burst length capability dt-bindings: dma: dw: Add max burst transaction length property dt-bindings: dma: dw: Convert DW DMAC to DT binding dmaengine: ti: k3-udma: Query throughput level information from hardware dmaengine: ti: k3-udma: Use defines for capabilities register parsing dmaengine: xilinx: dpdma: Fix kerneldoc warning dmaengine: xilinx: dpdma: add missing kernel doc dmaengine: xilinx: dpdma: remove comparison of unsigned expression ...
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@@ -8,10 +8,15 @@
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#ifndef _PLATFORM_DATA_DMA_DW_H
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#define _PLATFORM_DATA_DMA_DW_H
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#include <linux/device.h>
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#include <linux/bits.h>
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#include <linux/types.h>
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#define DW_DMA_MAX_NR_MASTERS 4
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#define DW_DMA_MAX_NR_CHANNELS 8
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#define DW_DMA_MIN_BURST 1
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#define DW_DMA_MAX_BURST 256
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struct device;
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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@@ -42,6 +47,8 @@ struct dw_dma_slave {
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* @data_width: Maximum data width supported by hardware per AHB master
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* (in bytes, power of 2)
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* @multi_block: Multi block transfers supported by hardware per channel.
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* @max_burst: Maximum value of burst transaction size supported by hardware
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* per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
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* @protctl: Protection control signals setting per channel.
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*/
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struct dw_dma_platform_data {
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@@ -56,6 +63,7 @@ struct dw_dma_platform_data {
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unsigned char nr_masters;
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unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
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unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS];
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u32 max_burst[DW_DMA_MAX_NR_CHANNELS];
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#define CHAN_PROTCTL_PRIVILEGED BIT(0)
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#define CHAN_PROTCTL_BUFFERABLE BIT(1)
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#define CHAN_PROTCTL_CACHEABLE BIT(2)
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