Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc driver specific updates from Olof Johansson: "These changes are specific to some driver that may be used by multiple boards or socs. The most significant change in here is the move of the samsung iommu code from a platform specific in-kernel interface to the generic iommu subsystem." Fix up trivial conflicts in arch/arm/mach-exynos/Kconfig * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits) mmc: dt: Consolidate DT bindings iommu/exynos: Add iommu driver for EXYNOS Platforms ARM: davinci: optimize the DMA ISR ARM: davinci: implement DEBUG_LL port choice ARM: tegra: Add SMMU enabler in AHB ARM: tegra: Add Tegra AHB driver Input: pxa27x_keypad add choice to set direct_key_mask Input: pxa27x_keypad direct key may be low active Input: pxa27x_keypad bug fix for direct_key_mask Input: pxa27x_keypad keep clock on as wakeup source ARM: dt: tegra: pinmux changes for USB ULPI ARM: tegra: add USB ULPI PHY reset GPIO to device tree ARM: tegra: don't hard-code USB ULPI PHY reset_gpio ARM: tegra: change pll_p_out4's rate to 24MHz ARM: tegra: fix pclk rate ARM: tegra: reparent sclk to pll_c_out1 ARM: tegra: Add pllc clock init table ARM: dt: tegra cardhu: basic audio support ARM: dt: tegra30.dtsi: Add audio-related nodes ARM: tegra: add AUXDATA required for audio ...
This commit is contained in:
Linus Torvalds
@@ -1,2 +1,2 @@
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obj-y += bus.o
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obj-$(CONFIG_ARM_AMBA) += bus.o
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obj-$(CONFIG_TEGRA_AHB) += tegra-ahb.o
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293
drivers/amba/tegra-ahb.c
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293
drivers/amba/tegra-ahb.c
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@@ -0,0 +1,293 @@
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2011 Google, Inc.
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*
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* Author:
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* Jay Cheng <jacheng@nvidia.com>
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* James Wylder <james.wylder@motorola.com>
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* Benoit Goby <benoit@android.com>
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* Colin Cross <ccross@android.com>
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* Hiroshi DOYU <hdoyu@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#define DRV_NAME "tegra-ahb"
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#define AHB_ARBITRATION_DISABLE 0x00
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#define AHB_ARBITRATION_PRIORITY_CTRL 0x04
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#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
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#define PRIORITY_SELECT_USB BIT(6)
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#define PRIORITY_SELECT_USB2 BIT(18)
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#define PRIORITY_SELECT_USB3 BIT(17)
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#define AHB_GIZMO_AHB_MEM 0x0c
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#define ENB_FAST_REARBITRATE BIT(2)
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#define DONT_SPLIT_AHB_WR BIT(7)
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#define AHB_GIZMO_APB_DMA 0x10
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#define AHB_GIZMO_IDE 0x18
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#define AHB_GIZMO_USB 0x1c
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#define AHB_GIZMO_AHB_XBAR_BRIDGE 0x20
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#define AHB_GIZMO_CPU_AHB_BRIDGE 0x24
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#define AHB_GIZMO_COP_AHB_BRIDGE 0x28
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#define AHB_GIZMO_XBAR_APB_CTLR 0x2c
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#define AHB_GIZMO_VCP_AHB_BRIDGE 0x30
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#define AHB_GIZMO_NAND 0x3c
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#define AHB_GIZMO_SDMMC4 0x44
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#define AHB_GIZMO_XIO 0x48
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#define AHB_GIZMO_BSEV 0x60
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#define AHB_GIZMO_BSEA 0x70
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#define AHB_GIZMO_NOR 0x74
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#define AHB_GIZMO_USB2 0x78
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#define AHB_GIZMO_USB3 0x7c
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#define IMMEDIATE BIT(18)
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#define AHB_GIZMO_SDMMC1 0x80
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#define AHB_GIZMO_SDMMC2 0x84
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#define AHB_GIZMO_SDMMC3 0x88
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#define AHB_MEM_PREFETCH_CFG_X 0xd8
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#define AHB_ARBITRATION_XBAR_CTRL 0xdc
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#define AHB_MEM_PREFETCH_CFG3 0xe0
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#define AHB_MEM_PREFETCH_CFG4 0xe4
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#define AHB_MEM_PREFETCH_CFG1 0xec
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#define AHB_MEM_PREFETCH_CFG2 0xf0
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#define PREFETCH_ENB BIT(31)
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#define MST_ID(x) (((x) & 0x1f) << 26)
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#define AHBDMA_MST_ID MST_ID(5)
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#define USB_MST_ID MST_ID(6)
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#define USB2_MST_ID MST_ID(18)
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#define USB3_MST_ID MST_ID(17)
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#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
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#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
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#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xf8
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#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
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static struct platform_driver tegra_ahb_driver;
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static const u32 tegra_ahb_gizmo[] = {
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AHB_ARBITRATION_DISABLE,
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AHB_ARBITRATION_PRIORITY_CTRL,
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AHB_GIZMO_AHB_MEM,
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AHB_GIZMO_APB_DMA,
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AHB_GIZMO_IDE,
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AHB_GIZMO_USB,
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AHB_GIZMO_AHB_XBAR_BRIDGE,
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AHB_GIZMO_CPU_AHB_BRIDGE,
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AHB_GIZMO_COP_AHB_BRIDGE,
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AHB_GIZMO_XBAR_APB_CTLR,
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AHB_GIZMO_VCP_AHB_BRIDGE,
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AHB_GIZMO_NAND,
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AHB_GIZMO_SDMMC4,
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AHB_GIZMO_XIO,
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AHB_GIZMO_BSEV,
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AHB_GIZMO_BSEA,
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AHB_GIZMO_NOR,
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AHB_GIZMO_USB2,
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AHB_GIZMO_USB3,
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AHB_GIZMO_SDMMC1,
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AHB_GIZMO_SDMMC2,
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AHB_GIZMO_SDMMC3,
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AHB_MEM_PREFETCH_CFG_X,
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AHB_ARBITRATION_XBAR_CTRL,
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AHB_MEM_PREFETCH_CFG3,
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AHB_MEM_PREFETCH_CFG4,
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AHB_MEM_PREFETCH_CFG1,
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AHB_MEM_PREFETCH_CFG2,
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AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
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};
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struct tegra_ahb {
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void __iomem *regs;
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struct device *dev;
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u32 ctx[0];
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};
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static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
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{
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return readl(ahb->regs + offset);
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}
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static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
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{
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writel(value, ahb->regs + offset);
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}
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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static int tegra_ahb_match_by_smmu(struct device *dev, void *data)
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{
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struct tegra_ahb *ahb = dev_get_drvdata(dev);
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struct device_node *dn = data;
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return (ahb->dev->of_node == dn) ? 1 : 0;
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}
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int tegra_ahb_enable_smmu(struct device_node *dn)
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{
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struct device *dev;
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u32 val;
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struct tegra_ahb *ahb;
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dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
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tegra_ahb_match_by_smmu);
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if (!dev)
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return -EPROBE_DEFER;
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ahb = dev_get_drvdata(dev);
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val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
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val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
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gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
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return 0;
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}
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EXPORT_SYMBOL(tegra_ahb_enable_smmu);
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#endif
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static int tegra_ahb_suspend(struct device *dev)
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{
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int i;
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struct tegra_ahb *ahb = dev_get_drvdata(dev);
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for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
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ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
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return 0;
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}
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static int tegra_ahb_resume(struct device *dev)
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{
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int i;
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struct tegra_ahb *ahb = dev_get_drvdata(dev);
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for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
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gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
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return 0;
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}
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static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
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tegra_ahb_suspend,
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tegra_ahb_resume, NULL);
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static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
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{
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u32 val;
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val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
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val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
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gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
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val = gizmo_readl(ahb, AHB_GIZMO_USB);
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val |= IMMEDIATE;
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gizmo_writel(ahb, val, AHB_GIZMO_USB);
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val = gizmo_readl(ahb, AHB_GIZMO_USB2);
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val |= IMMEDIATE;
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gizmo_writel(ahb, val, AHB_GIZMO_USB2);
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val = gizmo_readl(ahb, AHB_GIZMO_USB3);
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val |= IMMEDIATE;
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gizmo_writel(ahb, val, AHB_GIZMO_USB3);
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val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
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val |= PRIORITY_SELECT_USB |
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PRIORITY_SELECT_USB2 |
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PRIORITY_SELECT_USB3 |
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AHB_PRIORITY_WEIGHT(7);
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gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
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val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
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val &= ~MST_ID(~0);
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val |= PREFETCH_ENB |
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AHBDMA_MST_ID |
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ADDR_BNDRY(0xc) |
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INACTIVITY_TIMEOUT(0x1000);
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gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
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val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
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val &= ~MST_ID(~0);
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val |= PREFETCH_ENB |
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USB_MST_ID |
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ADDR_BNDRY(0xc) |
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INACTIVITY_TIMEOUT(0x1000);
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gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
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val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
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val &= ~MST_ID(~0);
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val |= PREFETCH_ENB |
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USB3_MST_ID |
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ADDR_BNDRY(0xc) |
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INACTIVITY_TIMEOUT(0x1000);
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gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
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val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
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val &= ~MST_ID(~0);
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val |= PREFETCH_ENB |
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USB2_MST_ID |
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ADDR_BNDRY(0xc) |
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INACTIVITY_TIMEOUT(0x1000);
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gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
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}
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static int __devinit tegra_ahb_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct tegra_ahb *ahb;
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size_t bytes;
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bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
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ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
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if (!ahb)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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ahb->regs = devm_request_and_ioremap(&pdev->dev, res);
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if (!ahb->regs)
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return -EBUSY;
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ahb->dev = &pdev->dev;
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platform_set_drvdata(pdev, ahb);
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tegra_ahb_gizmo_init(ahb);
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return 0;
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}
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static int __devexit tegra_ahb_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static const struct of_device_id tegra_ahb_of_match[] __devinitconst = {
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{ .compatible = "nvidia,tegra30-ahb", },
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{ .compatible = "nvidia,tegra20-ahb", },
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{},
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};
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static struct platform_driver tegra_ahb_driver = {
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.probe = tegra_ahb_probe,
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.remove = __devexit_p(tegra_ahb_remove),
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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.of_match_table = tegra_ahb_of_match,
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.pm = &tegra_ahb_pm,
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},
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};
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module_platform_driver(tegra_ahb_driver);
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MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
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MODULE_DESCRIPTION("Tegra AHB driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRV_NAME);
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