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Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull arm-soc driver specific updates from Olof Johansson:
 "These changes are specific to some driver that may be used by multiple
  boards or socs.  The most significant change in here is the move of
  the samsung iommu code from a platform specific in-kernel interface to
  the generic iommu subsystem."

Fix up trivial conflicts in arch/arm/mach-exynos/Kconfig

* tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
  mmc: dt: Consolidate DT bindings
  iommu/exynos: Add iommu driver for EXYNOS Platforms
  ARM: davinci: optimize the DMA ISR
  ARM: davinci: implement DEBUG_LL port choice
  ARM: tegra: Add SMMU enabler in AHB
  ARM: tegra: Add Tegra AHB driver
  Input: pxa27x_keypad add choice to set direct_key_mask
  Input: pxa27x_keypad direct key may be low active
  Input: pxa27x_keypad bug fix for direct_key_mask
  Input: pxa27x_keypad keep clock on as wakeup source
  ARM: dt: tegra: pinmux changes for USB ULPI
  ARM: tegra: add USB ULPI PHY reset GPIO to device tree
  ARM: tegra: don't hard-code USB ULPI PHY reset_gpio
  ARM: tegra: change pll_p_out4's rate to 24MHz
  ARM: tegra: fix pclk rate
  ARM: tegra: reparent sclk to pll_c_out1
  ARM: tegra: Add pllc clock init table
  ARM: dt: tegra cardhu: basic audio support
  ARM: dt: tegra30.dtsi: Add audio-related nodes
  ARM: tegra: add AUXDATA required for audio
  ...
This commit is contained in:
Linus Torvalds
2012-05-26 12:22:27 -07:00
parent 0877aa3908 046fae440d
commit ce53044c68
74 changed files with 2647 additions and 1032 deletions
Download Patch File Download Diff File Expand all files Collapse all files

71
arch/arm/mach-davinci/dma.c
View File

@@ -353,9 +353,10 @@ static int irq2ctlr(int irq)
*****************************************************************************/
static irqreturn_t dma_irq_handler(int irq, void *data)
{
int i;
int ctlr;
unsigned int cnt = 0;
u32 sh_ier;
u32 sh_ipr;
u32 bank;
ctlr = irq2ctlr(irq);
if (ctlr < 0)
@@ -363,41 +364,39 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
dev_dbg(data, "dma_irq_handler\n");
if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
(edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
return IRQ_NONE;
while (1) {
int j;
if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
edma_shadow0_read_array(ctlr, SH_IER, 0))
j = 0;
else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
edma_shadow0_read_array(ctlr, SH_IER, 1))
j = 1;
else
break;
dev_dbg(data, "IPR%d %08x\n", j,
edma_shadow0_read_array(ctlr, SH_IPR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
&& (edma_shadow0_read_array(ctlr,
SH_IER, j) & BIT(i))) {
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, j,
BIT(i));
if (edma_cc[ctlr]->intr_data[k].callback)
edma_cc[ctlr]->intr_data[k].callback(
k, DMA_COMPLETE,
edma_cc[ctlr]->intr_data[k].
data);
}
}
cnt++;
if (cnt > 10)
break;
sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
if (!sh_ipr) {
sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
if (!sh_ipr)
return IRQ_NONE;
sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
bank = 1;
} else {
sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
bank = 0;
}
do {
u32 slot;
u32 channel;
dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
slot = __ffs(sh_ipr);
sh_ipr &= ~(BIT(slot));
if (sh_ier & BIT(slot)) {
channel = (bank << 5) | slot;
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, bank,
BIT(slot));
if (edma_cc[ctlr]->intr_data[channel].callback)
edma_cc[ctlr]->intr_data[channel].callback(
channel, DMA_COMPLETE,
edma_cc[ctlr]->intr_data[channel].data);
}
} while (sh_ipr);
edma_shadow0_write(ctlr, SH_IEVAL, 1);
return IRQ_HANDLED;
}

58
arch/arm/mach-davinci/include/mach/debug-macro.S
View File

@@ -22,46 +22,28 @@
#define UART_SHIFT 2
.pushsection .data
davinci_uart_phys: .word 0
davinci_uart_virt: .word 0
.popsection
#if defined(CONFIG_DEBUG_DAVINCI_DMx_UART0)
#define UART_BASE DAVINCI_UART0_BASE
#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART0)
#define UART_BASE DA8XX_UART0_BASE
#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART1)
#define UART_BASE DA8XX_UART1_BASE
#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART2)
#define UART_BASE DA8XX_UART2_BASE
#elif defined(CONFIG_DEBUG_DAVINCI_TNETV107X_UART1)
#define UART_BASE TNETV107X_UART2_BASE
#define UART_VIRTBASE TNETV107X_UART2_VIRT
#else
#error "Select a specifc port for DEBUG_LL"
#endif
#ifndef UART_VIRTBASE
#define UART_VIRTBASE IO_ADDRESS(UART_BASE)
#endif
.macro addruart, rp, rv, tmp
/* Use davinci_uart_phys/virt if already configured */
10: adr \rp, 99f @ get effective addr of 99f
ldr \rv, [\rp] @ get absolute addr of 99f
sub \rv, \rv, \rp @ offset between the two
ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
sub \tmp, \rp, \rv @ make it effective
ldr \rp, [\tmp, #0] @ davinci_uart_phys
ldr \rv, [\tmp, #4] @ davinci_uart_virt
cmp \rp, #0 @ is port configured?
cmpne \rv, #0
bne 100f @ already configured
/* Check the debug UART address set in uncompress.h */
and \rp, pc, #0xff000000
ldr \rv, =DAVINCI_UART_INFO_OFS
add \rp, \rp, \rv
/* Copy uart phys address from decompressor uart info */
ldr \rv, [\rp, #0]
str \rv, [\tmp, #0]
/* Copy uart virt address from decompressor uart info */
ldr \rv, [\rp, #4]
str \rv, [\tmp, #4]
b 10b
.align
99: .word .
.word davinci_uart_phys
.ltorg
100:
ldr \rp, =UART_BASE
ldr \rv, =UART_VIRTBASE
.endm
.macro senduart,rd,rx

2
arch/arm/mach-davinci/include/mach/hardware.h
View File

@@ -22,7 +22,7 @@
/*
* I/O mapping
*/
#define IO_PHYS 0x01c00000UL
#define IO_PHYS UL(0x01c00000)
#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
#define IO_SIZE 0x00400000
#define IO_VIRT (IO_PHYS + IO_OFFSET)

10
arch/arm/mach-davinci/include/mach/serial.h
View File

@@ -15,16 +15,6 @@
#include <mach/hardware.h>
/*
* Stolen area that contains debug uart physical and virtual addresses. These
* addresses are filled in by the uncompress.h code, and are used by the debug
* macros in debug-macro.S.
*
* This area sits just below the page tables (see arch/arm/kernel/head.S).
* We define it as a relative offset from start of usable RAM.
*/
#define DAVINCI_UART_INFO_OFS 0x3ff8
#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)

30
arch/arm/mach-davinci/include/mach/uncompress.h
View File

@@ -43,37 +43,27 @@ static inline void flush(void)
barrier();
}
static inline void set_uart_info(u32 phys, void * __iomem virt)
static inline void set_uart_info(u32 phys)
{
/*
* Get address of some.bss variable and round it down
* a la CONFIG_AUTO_ZRELADDR.
*/
u32 ram_start = (u32)&uart & 0xf8000000;
u32 *uart_info = (u32 *)(ram_start + DAVINCI_UART_INFO_OFS);
uart = (u32 *)phys;
uart_info[0] = phys;
uart_info[1] = (u32)virt;
}
#define _DEBUG_LL_ENTRY(machine, phys, virt) \
if (machine_is_##machine()) { \
set_uart_info(phys, virt); \
break; \
#define _DEBUG_LL_ENTRY(machine, phys) \
{ \
if (machine_is_##machine()) { \
set_uart_info(phys); \
break; \
} \
}
#define DEBUG_LL_DAVINCI(machine, port) \
_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE, \
IO_ADDRESS(DAVINCI_UART##port##_BASE))
_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE)
#define DEBUG_LL_DA8XX(machine, port) \
_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE, \
IO_ADDRESS(DA8XX_UART##port##_BASE))
_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
#define DEBUG_LL_TNETV107X(machine, port) \
_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE, \
TNETV107X_UART##port##_VIRT)
_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
static inline void __arch_decomp_setup(unsigned long arch_id)
{