wcn36xx: only handle packets when ED or DONE bit is set
On RX and TX interrupts, check for the WCN36XX_CH_STAT_INT_ED_MASK or WCN36XX_CH_STAT_INT_DONE_MASK in the interrupt reason register, and only handle packets when it is set. This way, reap_tx_dxes() is only invoked when needed. This brings the dequeing logic in line with what the prima downstream driver is doing. While at it, also log the interrupt reason. Signed-off-by: Daniel Mack <daniel@zonque.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@@ -430,8 +430,12 @@ static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev)
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WCN36XX_INT_MASK_CHAN_TX_H);
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WCN36XX_INT_MASK_CHAN_TX_H);
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}
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}
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wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high\n");
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wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high, reason %08x\n",
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reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch);
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int_reason);
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if (int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK |
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WCN36XX_CH_STAT_INT_ED_MASK))
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reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch);
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}
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}
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if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) {
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if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) {
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@@ -465,8 +469,12 @@ static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev)
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WCN36XX_INT_MASK_CHAN_TX_L);
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WCN36XX_INT_MASK_CHAN_TX_L);
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}
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}
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wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low\n");
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wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low, reason %08x\n",
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reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch);
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int_reason);
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if (int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK |
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WCN36XX_CH_STAT_INT_ED_MASK))
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reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch);
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}
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}
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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@@ -545,6 +553,10 @@ static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn,
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WCN36XX_DXE_0_INT_ED_CLR,
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WCN36XX_DXE_0_INT_ED_CLR,
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int_mask);
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int_mask);
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if (!(int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK |
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WCN36XX_CH_STAT_INT_ED_MASK)))
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return 0;
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spin_lock(&ch->lock);
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spin_lock(&ch->lock);
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ctl = ch->head_blk_ctl;
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ctl = ch->head_blk_ctl;
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