MIPS: Alchemy: support multiple GPIO styles in one kernel
For GPIOLIB=y decide at runtime which gpiochips to register; in the GPIOLIB=n case, the gpio headers need to be reshuffled a bit to make multiple implementations coexist peacefully. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle

parent
2e8fd2e5ef
commit
ce1d43b9a9
@@ -347,17 +347,6 @@ static inline int alchemy_gpio2_to_irq(int gpio)
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/**********************************************************************/
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/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
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* SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
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* register enables use of GPIOs as wake source.
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*/
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static inline void alchemy_gpio1_input_enable(void)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
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__raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */
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wmb();
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}
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/* GPIO2 shared interrupts and control */
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static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
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@@ -561,6 +550,7 @@ static inline int alchemy_irq_to_gpio(int irq)
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#ifndef CONFIG_GPIOLIB
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#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000
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#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
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@@ -665,24 +655,7 @@ static inline void gpio_unexport(unsigned gpio)
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#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
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#else /* CONFIG GPIOLIB */
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/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
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#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
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/* get everything through gpiolib */
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#define gpio_to_irq __gpio_to_irq
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#define gpio_get_value __gpio_get_value
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#define gpio_set_value __gpio_set_value
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#define gpio_cansleep __gpio_cansleep
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#define irq_to_gpio alchemy_irq_to_gpio
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#include <asm-generic/gpio.h>
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#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
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#endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */
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#endif /* !CONFIG_GPIOLIB */
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