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drm/amdgpu:cg & pg shouldn't active on VF device

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CG & PG function changes engine clock/gating, which is
not appropriate for VF device, because one vf doesn't know
the whole picture of engine's overall workload.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu
2017-01-23 10:49:33 +08:00
committed by Alex Deucher
parent cbabc8b343
commit ce137c04ff
4 changed files with 27 additions and 0 deletions
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6
drivers/gpu/drm/amd/amdgpu/vi.c
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@@ -1391,6 +1391,9 @@ static int vi_common_set_clockgating_state(void *handle,
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (amdgpu_sriov_vf(adev))
return 0;
switch (adev->asic_type) {
case CHIP_FIJI:
vi_update_bif_medium_grain_light_sleep(adev,
@@ -1435,6 +1438,9 @@ static void vi_common_get_clockgating_state(void *handle, u32 *flags)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int data;
if (amdgpu_sriov_vf(adev))
*flags = 0;
/* AMD_CG_SUPPORT_BIF_LS */
data = RREG32_PCIE(ixPCIE_CNTL2);
if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)