Merge tag 'wireless-drivers-next-for-davem-2018-11-30' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next
Kalle Valo says: ==================== wireless-drivers-next patches for 4.21 First set of patches for 4.21. Most notable here is support for Quantenna's QSR1000/QSR2000 chipsets and more flexible ways to provide nvram files for brcmfmac. Major changes: brcmfmac * add support for first trying to get a board specific nvram file * add support for getting nvram contents from EFI variables qtnfmac * use single PCIe driver for all platforms and rename Kconfig option CONFIG_QTNFMAC_PEARL_PCIE to CONFIG_QTNFMAC_PCIE * add support for QSR1000/QSR2000 (Topaz) family of chipsets ath10k * add support for WCN3990 firmware crash recovery * add firmware memory dump support for QCA4019 wil6210 * add firmware error recovery while in AP mode ath9k * remove experimental notice from dynack feature iwlwifi * PCI IDs for some new 9000-series cards * improve antenna usage on connection problems * new firmware debugging infrastructure * some more work on 802.11ax * improve support for multiple RF modules with 22000 devices cordic * move cordic macros and defines to a public header file * convert brcmsmac and b43 to fully use cordic library ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
@@ -116,7 +116,7 @@ config ATH9K_DFS_CERTIFIED
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except increase code size.
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config ATH9K_DYNACK
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bool "Atheros ath9k ACK timeout estimation algorithm (EXPERIMENTAL)"
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bool "Atheros ath9k ACK timeout estimation algorithm"
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depends on ATH9K
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default n
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---help---
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@@ -586,7 +586,7 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
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REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
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break;
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}
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/* else: fall through */
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/* fall through */
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case 0x1:
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case 0x2:
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case 0x7:
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@@ -119,7 +119,7 @@ static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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aModeRefSel = 2;
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if (aModeRefSel)
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break;
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/* else: fall through */
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/* fall through */
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case 1:
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default:
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aModeRefSel = 0;
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@@ -1055,17 +1055,15 @@ void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
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static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done)
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{
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struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
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u32 new_flags, to_set, to_clear;
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u32 to_set, to_clear;
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if (!mci->update_2g5g || (mci->bt_state == MCI_BT_SLEEP))
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return;
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if (mci->is_2g) {
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new_flags = MCI_2G_FLAGS;
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to_clear = MCI_2G_FLAGS_CLEAR_MASK;
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to_set = MCI_2G_FLAGS_SET_MASK;
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} else {
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new_flags = MCI_5G_FLAGS;
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to_clear = MCI_5G_FLAGS_CLEAR_MASK;
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to_set = MCI_5G_FLAGS_SET_MASK;
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}
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@@ -272,7 +272,7 @@ struct ath_node {
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#endif
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u8 key_idx[4];
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u32 ackto;
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int ackto;
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struct list_head list;
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};
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@@ -29,9 +29,13 @@
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* ath_dynack_ewma - EWMA (Exponentially Weighted Moving Average) calculation
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*
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*/
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static inline u32 ath_dynack_ewma(u32 old, u32 new)
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static inline int ath_dynack_ewma(int old, int new)
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{
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return (new * (EWMA_DIV - EWMA_LEVEL) + old * EWMA_LEVEL) / EWMA_DIV;
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if (old > 0)
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return (new * (EWMA_DIV - EWMA_LEVEL) +
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old * EWMA_LEVEL) / EWMA_DIV;
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else
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return new;
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}
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/**
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@@ -82,10 +86,10 @@ static inline bool ath_dynack_bssidmask(struct ath_hw *ah, const u8 *mac)
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*/
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static void ath_dynack_compute_ackto(struct ath_hw *ah)
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{
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struct ath_node *an;
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u32 to = 0;
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struct ath_dynack *da = &ah->dynack;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_dynack *da = &ah->dynack;
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struct ath_node *an;
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int to = 0;
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list_for_each_entry(an, &da->nodes, list)
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if (an->ackto > to)
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@@ -144,7 +148,8 @@ static void ath_dynack_compute_to(struct ath_hw *ah)
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an->ackto = ath_dynack_ewma(an->ackto,
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ackto);
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ath_dbg(ath9k_hw_common(ah), DYNACK,
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"%pM to %u\n", dst, an->ackto);
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"%pM to %d [%u]\n", dst,
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an->ackto, ackto);
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if (time_is_before_jiffies(da->lto)) {
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ath_dynack_compute_ackto(ah);
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da->lto = jiffies + COMPUTE_TO;
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@@ -166,18 +171,21 @@ static void ath_dynack_compute_to(struct ath_hw *ah)
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* @ah: ath hw
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* @skb: socket buffer
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* @ts: tx status info
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* @sta: station pointer
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*
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*/
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void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
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struct ath_tx_status *ts)
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struct ath_tx_status *ts,
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struct ieee80211_sta *sta)
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{
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u8 ridx;
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struct ieee80211_hdr *hdr;
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struct ath_dynack *da = &ah->dynack;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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u32 dur = ts->duration;
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u8 ridx;
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if ((info->flags & IEEE80211_TX_CTL_NO_ACK) || !da->enabled)
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if (!da->enabled || (info->flags & IEEE80211_TX_CTL_NO_ACK))
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return;
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spin_lock_bh(&da->qlock);
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@@ -187,11 +195,19 @@ void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
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/* late ACK */
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if (ts->ts_status & ATH9K_TXERR_XRETRY) {
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if (ieee80211_is_assoc_req(hdr->frame_control) ||
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ieee80211_is_assoc_resp(hdr->frame_control)) {
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ieee80211_is_assoc_resp(hdr->frame_control) ||
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ieee80211_is_auth(hdr->frame_control)) {
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ath_dbg(common, DYNACK, "late ack\n");
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ath9k_hw_setslottime(ah, (LATEACK_TO - 3) / 2);
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ath9k_hw_set_ack_timeout(ah, LATEACK_TO);
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ath9k_hw_set_cts_timeout(ah, LATEACK_TO);
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if (sta) {
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struct ath_node *an;
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an = (struct ath_node *)sta->drv_priv;
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an->ackto = -1;
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}
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da->lto = jiffies + LATEACK_DELAY;
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}
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@@ -202,14 +218,13 @@ void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
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ridx = ts->ts_rateindex;
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da->st_rbf.ts[da->st_rbf.t_rb].tstamp = ts->ts_tstamp;
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da->st_rbf.ts[da->st_rbf.t_rb].dur = ts->duration;
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ether_addr_copy(da->st_rbf.addr[da->st_rbf.t_rb].h_dest, hdr->addr1);
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ether_addr_copy(da->st_rbf.addr[da->st_rbf.t_rb].h_src, hdr->addr2);
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if (!(info->status.rates[ridx].flags & IEEE80211_TX_RC_MCS)) {
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u32 phy, sifs;
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const struct ieee80211_rate *rate;
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struct ieee80211_tx_rate *rates = info->status.rates;
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u32 phy;
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rate = &common->sbands[info->band].bitrates[rates[ridx].idx];
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if (info->band == NL80211_BAND_2GHZ &&
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@@ -218,19 +233,18 @@ void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
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else
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phy = WLAN_RC_PHY_OFDM;
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sifs = ath_dynack_get_sifs(ah, phy);
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da->st_rbf.ts[da->st_rbf.t_rb].dur -= sifs;
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dur -= ath_dynack_get_sifs(ah, phy);
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}
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ath_dbg(common, DYNACK, "{%pM} tx sample %u [dur %u][h %u-t %u]\n",
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hdr->addr1, da->st_rbf.ts[da->st_rbf.t_rb].tstamp,
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da->st_rbf.ts[da->st_rbf.t_rb].dur, da->st_rbf.h_rb,
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(da->st_rbf.t_rb + 1) % ATH_DYN_BUF);
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da->st_rbf.ts[da->st_rbf.t_rb].dur = dur;
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INCR(da->st_rbf.t_rb, ATH_DYN_BUF);
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if (da->st_rbf.t_rb == da->st_rbf.h_rb)
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INCR(da->st_rbf.h_rb, ATH_DYN_BUF);
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ath_dbg(common, DYNACK, "{%pM} tx sample %u [dur %u][h %u-t %u]\n",
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hdr->addr1, ts->ts_tstamp, dur, da->st_rbf.h_rb,
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da->st_rbf.t_rb);
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ath_dynack_compute_to(ah);
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spin_unlock_bh(&da->qlock);
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@@ -251,20 +265,19 @@ void ath_dynack_sample_ack_ts(struct ath_hw *ah, struct sk_buff *skb,
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struct ath_common *common = ath9k_hw_common(ah);
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struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
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if (!ath_dynack_bssidmask(ah, hdr->addr1) || !da->enabled)
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if (!da->enabled || !ath_dynack_bssidmask(ah, hdr->addr1))
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return;
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spin_lock_bh(&da->qlock);
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da->ack_rbf.tstamp[da->ack_rbf.t_rb] = ts;
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ath_dbg(common, DYNACK, "rx sample %u [h %u-t %u]\n",
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da->ack_rbf.tstamp[da->ack_rbf.t_rb],
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da->ack_rbf.h_rb, (da->ack_rbf.t_rb + 1) % ATH_DYN_BUF);
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INCR(da->ack_rbf.t_rb, ATH_DYN_BUF);
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if (da->ack_rbf.t_rb == da->ack_rbf.h_rb)
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INCR(da->ack_rbf.h_rb, ATH_DYN_BUF);
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ath_dbg(common, DYNACK, "rx sample %u [h %u-t %u]\n",
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ts, da->ack_rbf.h_rb, da->ack_rbf.t_rb);
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ath_dynack_compute_to(ah);
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spin_unlock_bh(&da->qlock);
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@@ -86,7 +86,8 @@ void ath_dynack_node_deinit(struct ath_hw *ah, struct ath_node *an);
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void ath_dynack_init(struct ath_hw *ah);
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void ath_dynack_sample_ack_ts(struct ath_hw *ah, struct sk_buff *skb, u32 ts);
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void ath_dynack_sample_tx_ts(struct ath_hw *ah, struct sk_buff *skb,
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struct ath_tx_status *ts);
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struct ath_tx_status *ts,
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struct ieee80211_sta *sta);
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#else
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static inline void ath_dynack_init(struct ath_hw *ah) {}
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static inline void ath_dynack_node_init(struct ath_hw *ah,
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@@ -97,7 +98,8 @@ static inline void ath_dynack_sample_ack_ts(struct ath_hw *ah,
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struct sk_buff *skb, u32 ts) {}
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static inline void ath_dynack_sample_tx_ts(struct ath_hw *ah,
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struct sk_buff *skb,
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struct ath_tx_status *ts) {}
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struct ath_tx_status *ts,
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struct ieee80211_sta *sta) {}
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#endif
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#endif /* DYNACK_H */
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@@ -2279,6 +2279,7 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
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case NL80211_IFTYPE_ADHOC:
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REG_SET_BIT(ah, AR_TXCFG,
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AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
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/* fall through */
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case NL80211_IFTYPE_MESH_POINT:
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case NL80211_IFTYPE_AP:
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REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
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@@ -629,7 +629,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
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if (bf == bf->bf_lastbf)
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ath_dynack_sample_tx_ts(sc->sc_ah,
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bf->bf_mpdu,
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ts);
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ts, sta);
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}
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ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
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@@ -773,7 +773,8 @@ static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
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memcpy(info->control.rates, bf->rates,
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sizeof(info->control.rates));
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ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
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ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts);
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ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
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sta);
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}
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ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
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} else
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