ASoC: amd: dma driver changes for bt i2s instance
With in ACP, There are three I2S controllers can be configured/enabled ( I2S SP, I2S MICSP, I2S BT). Default enabled I2S controller instance is I2S SP. This patch provides required changes to support I2S BT controller Instance. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Este commit está contenido en:
Mukunda, Vijendar
cometido por
Mark Brown
Mark Brown
padre
839a12c799
commit
ccfbb4f572
@@ -37,12 +37,14 @@
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#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
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#define MIN_BUFFER MAX_BUFFER
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#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192
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#define ST_PLAYBACK_MAX_PERIOD_SIZE 4096
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#define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE
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#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
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#define ST_MIN_BUFFER ST_MAX_BUFFER
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#define DRV_NAME "acp_audio_dma"
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bool bt_uart_enable = true;
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EXPORT_SYMBOL(bt_uart_enable);
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static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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@@ -357,6 +359,9 @@ static void acp_dma_start(void __iomem *acp_mmio,
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case ACP_TO_I2S_DMA_CH_NUM:
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case ACP_TO_SYSRAM_CH_NUM:
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case I2S_TO_ACP_DMA_CH_NUM:
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case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
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case ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM:
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case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
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dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
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break;
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default:
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@@ -519,6 +524,13 @@ static int acp_init(void __iomem *acp_mmio, u32 asic_type)
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val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
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acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
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/* For BT instance change pins from UART to BT */
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if (!bt_uart_enable) {
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val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
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val |= ACP_BT_UART_PAD_SELECT_MASK;
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acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
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}
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/* initiailize Onion control DAGB register */
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acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
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mmACP_AXI2DAGB_ONION_CNTL);
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@@ -637,6 +649,24 @@ static irqreturn_t dma_irq_handler(int irq, void *arg)
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {
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valid_irq = true;
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if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_9) ==
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PLAYBACK_START_DMA_DESCR_CH9)
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dscr_idx = PLAYBACK_END_DMA_DESCR_CH8;
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else
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dscr_idx = PLAYBACK_START_DMA_DESCR_CH8;
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config_acp_dma_channel(acp_mmio,
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SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM,
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dscr_idx, 1, 0);
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acp_dma_start(acp_mmio, SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM,
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false);
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snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);
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acp_reg_write((intr_flag &
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BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
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valid_irq = true;
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if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) ==
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@@ -659,6 +689,31 @@ static irqreturn_t dma_irq_handler(int irq, void *arg)
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
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valid_irq = true;
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if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_11) ==
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CAPTURE_START_DMA_DESCR_CH11)
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dscr_idx = CAPTURE_END_DMA_DESCR_CH10;
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else
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dscr_idx = CAPTURE_START_DMA_DESCR_CH10;
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config_acp_dma_channel(acp_mmio,
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ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
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dscr_idx, 1, 0);
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acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
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false);
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acp_reg_write((intr_flag &
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BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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if ((intr_flag & BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) != 0) {
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valid_irq = true;
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snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
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acp_reg_write((intr_flag &
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BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) << 16,
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acp_mmio, mmACP_EXTERNAL_INTR_STAT);
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}
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if (valid_irq)
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return IRQ_HANDLED;
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else
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@@ -714,11 +769,11 @@ static int acp_dma_open(struct snd_pcm_substream *substream)
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* This enablement is not required for another stream, if current
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* stream is not closed
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*/
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if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream)
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if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&
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!intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream)
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acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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intr_data->play_i2ssp_stream = substream;
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/*
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* For Stoney, Memory gating is disabled,i.e SRAM Banks
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* won't be turned off. The default state for SRAM banks is ON.
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@@ -730,7 +785,6 @@ static int acp_dma_open(struct snd_pcm_substream *substream)
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bank, true);
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}
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} else {
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intr_data->capture_i2ssp_stream = substream;
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if (intr_data->asic_type != CHIP_STONEY) {
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for (bank = 5; bank <= 8; bank++)
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acp_set_sram_bank_state(intr_data->acp_mmio,
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@@ -754,6 +808,8 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
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DRV_NAME);
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struct audio_drv_data *adata = dev_get_drvdata(component->dev);
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struct snd_soc_card *card = prtd->card;
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struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);
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runtime = substream->runtime;
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rtd = runtime->private_data;
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@@ -761,52 +817,109 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream,
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if (WARN_ON(!rtd))
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return -EINVAL;
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rtd->i2s_instance = pinfo->i2s_instance;
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if (adata->asic_type == CHIP_STONEY) {
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val = acp_reg_read(adata->acp_mmio,
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mmACP_I2S_16BIT_RESOLUTION_EN);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
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else
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val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
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break;
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case I2S_SP_INSTANCE:
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default:
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val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
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}
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} else {
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
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break;
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case I2S_SP_INSTANCE:
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default:
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val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
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}
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}
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acp_reg_write(val, adata->acp_mmio,
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mmACP_I2S_16BIT_RESOLUTION_EN);
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (adata->asic_type) {
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case CHIP_STONEY:
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rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;
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rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;
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rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;
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rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;
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rtd->destination = TO_BLUETOOTH;
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rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;
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rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;
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rtd->byte_cnt_high_reg_offset =
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mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;
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rtd->byte_cnt_low_reg_offset =
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mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;
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adata->play_i2sbt_stream = substream;
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break;
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case I2S_SP_INSTANCE:
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default:
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rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
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switch (adata->asic_type) {
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case CHIP_STONEY:
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rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
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break;
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default:
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rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
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}
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rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
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rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
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rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
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rtd->destination = TO_ACP_I2S_1;
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rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
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rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
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rtd->byte_cnt_high_reg_offset =
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mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
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rtd->byte_cnt_low_reg_offset =
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mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
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adata->play_i2ssp_stream = substream;
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}
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rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
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rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
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rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
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rtd->destination = TO_ACP_I2S_1;
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rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
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rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
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rtd->byte_cnt_high_reg_offset =
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mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
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rtd->byte_cnt_low_reg_offset = mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
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} else {
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switch (adata->asic_type) {
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case CHIP_STONEY:
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rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
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rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
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rtd->ch1 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
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rtd->ch2 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
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rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
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rtd->destination = FROM_BLUETOOTH;
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rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
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rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;
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rtd->byte_cnt_high_reg_offset =
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mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;
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rtd->byte_cnt_low_reg_offset =
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mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;
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adata->capture_i2sbt_stream = substream;
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break;
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case I2S_SP_INSTANCE:
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default:
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rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
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rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
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rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
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rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
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switch (adata->asic_type) {
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case CHIP_STONEY:
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rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
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rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
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break;
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default:
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rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
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rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
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}
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rtd->destination = FROM_ACP_I2S_1;
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rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
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rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
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rtd->byte_cnt_high_reg_offset =
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mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
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rtd->byte_cnt_low_reg_offset =
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mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
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adata->capture_i2ssp_stream = substream;
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}
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rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
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rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
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rtd->destination = FROM_ACP_I2S_1;
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rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
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rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
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rtd->byte_cnt_high_reg_offset =
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mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
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rtd->byte_cnt_low_reg_offset = mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
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}
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size = params_buffer_bytes(params);
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@@ -999,24 +1112,39 @@ static int acp_dma_close(struct snd_pcm_substream *substream)
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struct audio_drv_data *adata = dev_get_drvdata(component->dev);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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adata->play_i2ssp_stream = NULL;
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/*
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* For Stoney, Memory gating is disabled,i.e SRAM Banks
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* won't be turned off. The default state for SRAM banks is ON.
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* Setting SRAM bank state code skipped for STONEY platform.
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* added condition checks for Carrizo platform only
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*/
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if (adata->asic_type != CHIP_STONEY) {
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for (bank = 1; bank <= 4; bank++)
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acp_set_sram_bank_state(adata->acp_mmio, bank,
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false);
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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adata->play_i2sbt_stream = NULL;
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break;
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case I2S_SP_INSTANCE:
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default:
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adata->play_i2ssp_stream = NULL;
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/*
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* For Stoney, Memory gating is disabled,i.e SRAM Banks
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* won't be turned off. The default state for SRAM banks
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* is ON.Setting SRAM bank state code skipped for STONEY
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* platform. Added condition checks for Carrizo platform
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* only.
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*/
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if (adata->asic_type != CHIP_STONEY) {
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for (bank = 1; bank <= 4; bank++)
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acp_set_sram_bank_state(adata->acp_mmio,
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bank, false);
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}
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}
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} else {
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adata->capture_i2ssp_stream = NULL;
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if (adata->asic_type != CHIP_STONEY) {
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for (bank = 5; bank <= 8; bank++)
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acp_set_sram_bank_state(adata->acp_mmio, bank,
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false);
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switch (rtd->i2s_instance) {
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case I2S_BT_INSTANCE:
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adata->capture_i2sbt_stream = NULL;
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break;
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case I2S_SP_INSTANCE:
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default:
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adata->capture_i2ssp_stream = NULL;
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if (adata->asic_type != CHIP_STONEY) {
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for (bank = 5; bank <= 8; bank++)
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acp_set_sram_bank_state(adata->acp_mmio,
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bank, false);
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}
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}
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}
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@@ -1024,7 +1152,8 @@ static int acp_dma_close(struct snd_pcm_substream *substream)
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* Disable ACP irq, when the current stream is being closed and
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* another stream is also not active.
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*/
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if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream)
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if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&
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!adata->play_i2sbt_stream && !adata->capture_i2sbt_stream)
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acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
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kfree(rtd);
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return 0;
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@@ -1078,6 +1207,8 @@ static int acp_audio_probe(struct platform_device *pdev)
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audio_drv_data->play_i2ssp_stream = NULL;
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audio_drv_data->capture_i2ssp_stream = NULL;
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audio_drv_data->play_i2sbt_stream = NULL;
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audio_drv_data->capture_i2sbt_stream = NULL;
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audio_drv_data->asic_type = *pdata;
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@@ -1134,6 +1265,7 @@ static int acp_pcm_resume(struct device *dev)
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{
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u16 bank;
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int status;
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struct audio_substream_data *rtd;
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struct audio_drv_data *adata = dev_get_drvdata(dev);
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status = acp_init(adata->acp_mmio, adata->asic_type);
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@@ -1153,9 +1285,8 @@ static int acp_pcm_resume(struct device *dev)
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acp_set_sram_bank_state(adata->acp_mmio, bank,
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true);
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}
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config_acp_dma(adata->acp_mmio,
|
||||
adata->play_i2ssp_stream->runtime->private_data,
|
||||
adata->asic_type);
|
||||
rtd = adata->play_i2ssp_stream->runtime->private_data;
|
||||
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
|
||||
}
|
||||
if (adata->capture_i2ssp_stream &&
|
||||
adata->capture_i2ssp_stream->runtime) {
|
||||
@@ -1164,9 +1295,20 @@ static int acp_pcm_resume(struct device *dev)
|
||||
acp_set_sram_bank_state(adata->acp_mmio, bank,
|
||||
true);
|
||||
}
|
||||
config_acp_dma(adata->acp_mmio,
|
||||
adata->capture_i2ssp_stream->runtime->private_data,
|
||||
adata->asic_type);
|
||||
rtd = adata->capture_i2ssp_stream->runtime->private_data;
|
||||
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
|
||||
}
|
||||
if (adata->asic_type != CHIP_CARRIZO) {
|
||||
if (adata->play_i2sbt_stream &&
|
||||
adata->play_i2sbt_stream->runtime) {
|
||||
rtd = adata->play_i2sbt_stream->runtime->private_data;
|
||||
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
|
||||
}
|
||||
if (adata->capture_i2sbt_stream &&
|
||||
adata->capture_i2sbt_stream->runtime) {
|
||||
rtd = adata->capture_i2sbt_stream->runtime->private_data;
|
||||
config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
|
||||
}
|
||||
}
|
||||
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
|
||||
return 0;
|
||||
|
||||
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