x86/bugs, KVM: Extend speculation control for VIRT_SPEC_CTRL
AMD is proposing a VIRT_SPEC_CTRL MSR to handle the Speculative Store Bypass Disable via MSR_AMD64_LS_CFG so that guests do not have to care about the bit position of the SSBD bit and thus facilitate migration. Also, the sibling coordination on Family 17H CPUs can only be done on the host. Extend x86_spec_ctrl_set_guest() and x86_spec_ctrl_restore_host() with an extra argument for the VIRT_SPEC_CTRL MSR. Hand in 0 from VMX and in SVM add a new virt_spec_ctrl member to the CPU data structure which is going to be used in later patches for the actual implementation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov <bp@suse.de> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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@@ -151,7 +151,15 @@ u64 x86_spec_ctrl_get_default(void)
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}
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
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void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
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/**
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* x86_spec_ctrl_set_guest - Set speculation control registers for the guest
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* @guest_spec_ctrl: The guest content of MSR_SPEC_CTRL
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* @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL
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* (may get translated to MSR_AMD64_LS_CFG bits)
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*
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* Avoids writing to the MSR if the content/bits are the same
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*/
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void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
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{
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u64 host = x86_spec_ctrl_base;
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@@ -168,7 +176,15 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
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}
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest);
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void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
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/**
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* x86_spec_ctrl_restore_host - Restore host speculation control registers
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* @guest_spec_ctrl: The guest content of MSR_SPEC_CTRL
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* @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL
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* (may get translated to MSR_AMD64_LS_CFG bits)
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*
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* Avoids writing to the MSR if the content/bits are the same
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*/
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void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
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{
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u64 host = x86_spec_ctrl_base;
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