Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux into next
Pull arm64 updates from Catalin Marinas: - Optimised assembly string/memory routines (based on the AArch64 Cortex Strings library contributed to glibc but re-licensed under GPLv2) - Optimised crypto algorithms making use of the ARMv8 crypto extensions (together with kernel API for using FPSIMD instructions in interrupt context) - Ftrace support - CPU topology parsing from DT - ESR_EL1 (Exception Syndrome Register) exposed to user space signal handlers for SIGSEGV/SIGBUS (useful to emulation tools like Qemu) - 1GB section linear mapping if applicable - Barriers usage clean-up - Default pgprot clean-up Conflicts as per Catalin. * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (57 commits) arm64: kernel: initialize broadcast hrtimer based clock event device arm64: ftrace: Add system call tracepoint arm64: ftrace: Add CALLER_ADDRx macros arm64: ftrace: Add dynamic ftrace support arm64: Add ftrace support ftrace: Add arm64 support to recordmcount arm64: Add 'notrace' attribute to unwind_frame() for ftrace arm64: add __ASSEMBLY__ in asm/insn.h arm64: Fix linker script entry point arm64: lib: Implement optimized string length routines arm64: lib: Implement optimized string compare routines arm64: lib: Implement optimized memcmp routine arm64: lib: Implement optimized memset routine arm64: lib: Implement optimized memmove routine arm64: lib: Implement optimized memcpy routine arm64: defconfig: enable a few more common/useful options in defconfig ftrace: Make CALLER_ADDRx macros more generic arm64: Fix deadlock scenario with smp_send_stop() arm64: Fix machine_shutdown() definition arm64: Support arch_irq_work_raise() via self IPIs ...
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@@ -25,6 +25,7 @@
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#include <linux/utsname.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/cache.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/screen_info.h>
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@@ -200,6 +201,8 @@ static void __init setup_processor(void)
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{
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struct cpu_info *cpu_info;
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u64 features, block;
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u32 cwg;
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int cls;
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cpu_info = lookup_processor_type(read_cpuid_id());
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if (!cpu_info) {
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@@ -216,6 +219,18 @@ static void __init setup_processor(void)
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sprintf(init_utsname()->machine, ELF_PLATFORM);
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elf_hwcap = 0;
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/*
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* Check for sane CTR_EL0.CWG value.
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*/
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cwg = cache_type_cwg();
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cls = cache_line_size();
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if (!cwg)
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pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
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cls);
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if (L1_CACHE_BYTES < cls)
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pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
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L1_CACHE_BYTES, cls);
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/*
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* ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
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* The blocks we test below represent incremental functionality
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@@ -363,7 +378,6 @@ void __init setup_arch(char **cmdline_p)
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*cmdline_p = boot_command_line;
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init_mem_pgprot();
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early_ioremap_init();
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parse_early_param();
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