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rapidio/tsi721: add PCIe MRRS override parameter

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Add PCIe Maximum Read Request Size (MRRS) adjustment parameter to allow
users to override configuration register value set during PCIe bus
initialization.

Performance of Tsi721 device as PCIe bus master can be improved if MRRS
is set to its maximum value (4096 bytes).  Some platforms have
limitations for supported MRRS and therefore the default value should be
preserved, unless it is known that given platform supports full set of
MRRS values defined by PCI Express specification.

Link: http://lkml.kernel.org/r/1469125134-16523-6-git-send-email-alexandre.bounine@idt.com
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Cc: Andre van Herk <andre.van.herk@prodrive-technologies.com>
Cc: Barry Wood <barry.wood@idt.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Alexandre Bounine
2016-08-02 14:06:40 -07:00
committed by Linus Torvalds
parent 4498c31adf
commit cb782cdd2f
2 changed files with 22 additions and 1 deletions
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16
drivers/rapidio/devices/tsi721.c
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@@ -37,11 +37,15 @@
#include "tsi721.h"
#ifdef DEBUG
u32 dbg_level = DBG_INIT | DBG_EXIT;
u32 dbg_level;
module_param(dbg_level, uint, S_IWUSR | S_IRUGO);
MODULE_PARM_DESC(dbg_level, "Debugging output level (default 0 = none)");
#endif
static int pcie_mrrs = -1;
module_param(pcie_mrrs, int, S_IRUGO);
MODULE_PARM_DESC(pcie_mrrs, "PCIe MRRS override value (0...5)");
static void tsi721_omsg_handler(struct tsi721_device *priv, int ch);
static void tsi721_imsg_handler(struct tsi721_device *priv, int ch);
@@ -2840,6 +2844,16 @@ static int tsi721_probe(struct pci_dev *pdev,
pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
/* Override PCIe Maximum Read Request Size setting if requested */
if (pcie_mrrs >= 0) {
if (pcie_mrrs <= 5)
pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_READRQ, pcie_mrrs << 12);
else
tsi_info(&pdev->dev,
"Invalid MRRS override value %d", pcie_mrrs);
}
/* Adjust PCIe completion timeout. */
pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2);