Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "The large diff this time around is from the addition of a new clk driver for the TI Davinci family of SoCs. So far those clks have been supported with a custom implementation of the clk API in the arch port instead of in the CCF. With this driver merged we're one step closer to having a single clk API implementation. The other large diff is from the Amlogic clk driver that underwent some major surgery to use regmap. Beyond that, the biggest hitter is Samsung which needed some reworks to properly handle clk provider power domains and a bunch of PLL rate updates. The core framework was fairly quiet this round, just getting some cleanups and small fixes for some of the more esoteric features. And the usual set of driver non-critical fixes, cleanups, and minor additions are here as well. Core: - Rejig clk_ops::init() to be a little earlier for phase/accuracy ops - debugfs ops macroized to shave some lines of boilerplate code - Always calculate the phase instead of caching it in clk_get_phase() - More __must_check on bulk clk APIs New Drivers: - TI's Davinci family of SoCs - Intel's Stratix10 SoC - stm32mp157 SoC - Allwinner H6 CCU - Silicon Labs SI544 clock generator chip - Renesas R-Car M3-N and V3H SoCs - i.MX6SLL SoCs Removed Drivers: - ST-Ericsson AB8540/9540 Updates: - Mediatek MT2701 and MT7622 audsys support and MT2712 updates - STM32F469 DSI and STM32F769 sdmmc2 support - GPIO clks can sleep now - Spreadtrum SC9860 RTC clks - Nvidia Tegra MBIST workarounds and various minor fixes - Rockchip phase handling fixes and a memory leak plugged - Renesas drivers switch to readl/writel from clk_readl/clk_writel - Renesas gained CPU (Z/Z2) and watchdog support - Rockchip rk3328 display clks and rk3399 1.6GHz PLL support - Qualcomm PM8921 PMIC XO buffers - Amlogic migrates to regmap APIs - TI Keystone clk latching support - Allwinner H3 and H5 video clk fixes - Broadcom BCM2835 PLLs needed another bit to enable - i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix - i.MX6UL/ULL epdc_podf support - Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (233 commits) clk: davinci: add a reset lookup table for psc0 clk: imx: add clock driver for imx6sll dt-bindings: imx: update clock doc for imx6sll clk: imx: add new gate/gate2 wrapper funtion clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux clk: cs2000: set pm_ops in hibernate-compatible way clk: bcm2835: De-assert/assert PLL reset signal when appropriate clk: imx7d: Move clks_init_on before any clock operations clk: imx7d: Correct ahb clk parent select clk: imx7d: Correct dram pll type clk: imx7d: Add USB clock information clk: socfpga: stratix10: add clock driver for Stratix10 platform dt-bindings: documentation: add clock bindings information for Stratix10 clk: ti: fix flag space conflict with clkctrl clocks clk: uniphier: add additional ethernet clock lines for Pro4 clk: uniphier: add SATA clock control support clk: uniphier: add PCIe clock control support clk: Add driver for the si544 clock generator chip clk: davinci: Remove redundant dev_err calls clk: uniphier: add ethernet clock control support for PXs3 ...
This commit is contained in:
Linus Torvalds
@@ -22,6 +22,7 @@ obj-$(CONFIG_SOC_IMX35) += clk-imx35.o
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obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o
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obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o
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obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o
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obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o
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obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o
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obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
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obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
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@@ -101,7 +101,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
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init.name = name;
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init.ops = &clk_busy_divider_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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@@ -175,7 +175,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
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init.name = name;
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init.ops = &clk_busy_mux_ops;
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init.flags = 0;
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init.flags = CLK_IS_CRITICAL;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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340
drivers/clk/imx/clk-imx6sll.c
Normal file
340
drivers/clk/imx/clk-imx6sll.c
Normal file
@@ -0,0 +1,340 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP.
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*/
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#include <dt-bindings/clock/imx6sll-clock.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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#define CCM_ANALOG_PLL_BYPASS (0x1 << 16)
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#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
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#define xPLL_CLR(offset) (offset + 0x8)
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static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
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static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
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static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
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static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
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static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
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static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
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static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
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static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
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static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
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static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
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static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
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static const char *axi_sels[] = {"periph", "axi_alt_sel", };
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static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
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static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
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static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
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static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
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static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
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static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
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static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *ssi_sels[] = {"pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", "dummy",};
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static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
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static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
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static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
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static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
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static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
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static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
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static const char *ecspi_sels[] = { "pll3_60m", "osc", };
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static const char *uart_sels[] = { "pll3_80m", "osc", };
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static const char *perclk_sels[] = { "ipg", "osc", };
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static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
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static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static struct clk *clks[IMX6SLL_CLK_END];
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static struct clk_onecell_data clk_data;
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static const struct clk_div_table post_div_table[] = {
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{ .val = 2, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 0, .div = 4, },
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{ }
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};
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static const struct clk_div_table video_div_table[] = {
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{ .val = 0, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 2, .div = 1, },
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{ .val = 3, .div = 4, },
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{ }
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};
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static u32 share_count_audio;
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static u32 share_count_ssi1;
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static u32 share_count_ssi2;
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static u32 share_count_ssi3;
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static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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clks[IMX6SLL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clks[IMX6SLL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
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clks[IMX6SLL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
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/* ipp_di clock is external input */
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clks[IMX6SLL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
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clks[IMX6SLL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");
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base = of_iomap(np, 0);
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WARN_ON(!base);
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/* Do not bypass PLLs initially */
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writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0));
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writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10));
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writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20));
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writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30));
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writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70));
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writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0));
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writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xe0));
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clks[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6SLL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6SLL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6SLL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6SLL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6SLL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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clks[IMX6SLL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
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clks[IMX6SLL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
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clks[IMX6SLL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
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clks[IMX6SLL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
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clks[IMX6SLL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
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clks[IMX6SLL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
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clks[IMX6SLL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
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clks[IMX6SLL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6SLL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6SLL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6SLL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6SLL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6SLL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6SLL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
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clks[IMX6SLL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
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clks[IMX6SLL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
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clks[IMX6SLL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
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clks[IMX6SLL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
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clks[IMX6SLL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
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clks[IMX6SLL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
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clks[IMX6SLL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
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/*
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* Bit 20 is the reserved and read-only bit, we do this only for:
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* - Do nothing for usbphy clk_enable/disable
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* - Keep refcount when do usbphy clk_enable/disable, in that case,
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* the clk framework many need to enable/disable usbphy's parent
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*/
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clks[IMX6SLL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
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clks[IMX6SLL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
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/*
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* usbphy*_gate needs to be on after system boots up, and software
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* never needs to control it anymore.
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*/
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if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
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clks[IMX6SLL_CLK_USBPHY1_GATE] = imx_clk_gate_flags("usbphy1_gate", "dummy", base + 0x10, 6, CLK_IS_CRITICAL);
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clks[IMX6SLL_CLK_USBPHY2_GATE] = imx_clk_gate_flags("usbphy2_gate", "dummy", base + 0x20, 6, CLK_IS_CRITICAL);
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}
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/* name parent_name reg idx */
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clks[IMX6SLL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
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clks[IMX6SLL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
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clks[IMX6SLL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
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clks[IMX6SLL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
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clks[IMX6SLL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
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clks[IMX6SLL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
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clks[IMX6SLL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
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clks[IMX6SLL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
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clks[IMX6SLL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clks[IMX6SLL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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clks[IMX6SLL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clks[IMX6SLL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
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CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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/* name parent_name mult div */
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clks[IMX6SLL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
|
||||
clks[IMX6SLL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
|
||||
clks[IMX6SLL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clks[IMX6SLL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
|
||||
np = ccm_node;
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
||||
clks[IMX6SLL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clks[IMX6SLL_CLK_PLL1_SW] = imx_clk_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
|
||||
clks[IMX6SLL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
|
||||
clks[IMX6SLL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0);
|
||||
clks[IMX6SLL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clks[IMX6SLL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
|
||||
clks[IMX6SLL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clks[IMX6SLL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clks[IMX6SLL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clks[IMX6SLL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clks[IMX6SLL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
|
||||
clks[IMX6SLL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
|
||||
clks[IMX6SLL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
|
||||
clks[IMX6SLL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
|
||||
clks[IMX6SLL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
|
||||
clks[IMX6SLL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
|
||||
clks[IMX6SLL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
|
||||
clks[IMX6SLL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x30, 7, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
|
||||
clks[IMX6SLL_CLK_EPDC_PRE_SEL] = imx_clk_mux("epdc_pre_sel", base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels));
|
||||
clks[IMX6SLL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
|
||||
clks[IMX6SLL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
|
||||
clks[IMX6SLL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
|
||||
clks[IMX6SLL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
|
||||
|
||||
clks[IMX6SLL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clks[IMX6SLL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
|
||||
clks[IMX6SLL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clks[IMX6SLL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clks[IMX6SLL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clks[IMX6SLL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3);
|
||||
clks[IMX6SLL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
|
||||
clks[IMX6SLL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
|
||||
clks[IMX6SLL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clks[IMX6SLL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clks[IMX6SLL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
|
||||
clks[IMX6SLL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
|
||||
clks[IMX6SLL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
|
||||
clks[IMX6SLL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
|
||||
clks[IMX6SLL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
|
||||
clks[IMX6SLL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
|
||||
clks[IMX6SLL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
|
||||
clks[IMX6SLL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clks[IMX6SLL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clks[IMX6SLL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x30, 12, 3);
|
||||
clks[IMX6SLL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x30, 9, 3);
|
||||
clks[IMX6SLL_CLK_EPDC_PODF] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3);
|
||||
clks[IMX6SLL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
|
||||
clks[IMX6SLL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
|
||||
|
||||
clks[IMX6SLL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clks[IMX6SLL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clks[IMX6SLL_CLK_AXI_PODF] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clks[IMX6SLL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
|
||||
clks[IMX6SLL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clks[IMX6SLL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
|
||||
clks[IMX6SLL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clks[IMX6SLL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
|
||||
|
||||
clks[IMX6SLL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
|
||||
clks[IMX6SLL_CLK_LDB_DI1_SEL] = imx_clk_mux("ldb_di1_sel", base + 0x1c, 7, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels));
|
||||
clks[IMX6SLL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
|
||||
clks[IMX6SLL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1_div_sel", base + 0x20, 10, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
|
||||
|
||||
/* CCGR0 */
|
||||
clks[IMX6SLL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_DCP] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10);
|
||||
clks[IMX6SLL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
|
||||
clks[IMX6SLL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
|
||||
|
||||
/* CCGR1 */
|
||||
clks[IMX6SLL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
|
||||
clks[IMX6SLL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
|
||||
clks[IMX6SLL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
|
||||
clks[IMX6SLL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
|
||||
clks[IMX6SLL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10);
|
||||
clks[IMX6SLL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10);
|
||||
clks[IMX6SLL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
|
||||
clks[IMX6SLL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
|
||||
clks[IMX6SLL_CLK_GPT_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20);
|
||||
clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
|
||||
clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
|
||||
clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
|
||||
|
||||
/* CCGR2 */
|
||||
clks[IMX6SLL_CLK_CSI] = imx_clk_gate2("csi", "axi", base + 0x70, 2);
|
||||
clks[IMX6SLL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
|
||||
clks[IMX6SLL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
|
||||
clks[IMX6SLL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
|
||||
clks[IMX6SLL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
|
||||
clks[IMX6SLL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
|
||||
clks[IMX6SLL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
|
||||
|
||||
/* CCGR3 */
|
||||
clks[IMX6SLL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2);
|
||||
clks[IMX6SLL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2);
|
||||
clks[IMX6SLL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4);
|
||||
clks[IMX6SLL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4);
|
||||
clks[IMX6SLL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
|
||||
clks[IMX6SLL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
|
||||
clks[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_OCRAM] = imx_clk_gate_flags("ocram","ahb", base + 0x74, 28, CLK_IS_CRITICAL);
|
||||
|
||||
/* CCGR4 */
|
||||
clks[IMX6SLL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
|
||||
clks[IMX6SLL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
|
||||
clks[IMX6SLL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
|
||||
clks[IMX6SLL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
|
||||
|
||||
/* CCGR5 */
|
||||
clks[IMX6SLL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
|
||||
clks[IMX6SLL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clks[IMX6SLL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10);
|
||||
clks[IMX6SLL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6SLL_CLK_EXTERN_AUDIO] = imx_clk_gate2_shared("extern_audio", "extern_audio_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SLL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SLL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SLL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SLL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SLL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SLL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SLL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
|
||||
clks[IMX6SLL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
clks[IMX6SLL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24);
|
||||
clks[IMX6SLL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24);
|
||||
|
||||
/* CCGR6 */
|
||||
clks[IMX6SLL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clks[IMX6SLL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clks[IMX6SLL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clks[IMX6SLL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
|
||||
/* mask handshake of mmdc */
|
||||
writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + 0x4);
|
||||
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
/* Lower the AHB clock rate before changing the clock source. */
|
||||
clk_set_rate(clks[IMX6SLL_CLK_AHB], 99000000);
|
||||
|
||||
/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
|
||||
clk_set_parent(clks[IMX6SLL_CLK_PERIPH_CLK2_SEL], clks[IMX6SLL_CLK_PLL3_USB_OTG]);
|
||||
clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_CLK2]);
|
||||
clk_set_parent(clks[IMX6SLL_CLK_PERIPH_PRE], clks[IMX6SLL_CLK_PLL2_BUS]);
|
||||
clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_PRE]);
|
||||
|
||||
clk_set_rate(clks[IMX6SLL_CLK_AHB], 132000000);
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init);
|
||||
@@ -63,17 +63,17 @@ static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_d
|
||||
static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
|
||||
static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
|
||||
static const char *cko1_sels[] = {
|
||||
"pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
|
||||
"dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix",
|
||||
"epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
|
||||
"dummy", "dummy", "dummy", "dummy",
|
||||
"vadc", "ocram", "qspi2", "m4", "enet_ahb", "lcdif2_pix",
|
||||
"lcdif1_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
|
||||
};
|
||||
static const char *cko2_sels[] = {
|
||||
"dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
|
||||
"ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
|
||||
"lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core",
|
||||
"usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy",
|
||||
"dummy", "dummy", "dummy", "esai_extal", "eim_slow", "uart_serial",
|
||||
"spdif", "asrc", "dummy",
|
||||
"display_axi", "dummy", "osc", "dummy", "dummy",
|
||||
"usdhc2", "ssi1", "ssi2", "ssi3", "gpu_axi_podf", "dummy",
|
||||
"can_podf", "lvds1_out", "qspi1", "esai_extal", "eim_slow",
|
||||
"uart_serial", "spdif", "audio", "dummy",
|
||||
};
|
||||
static const char *cko_sels[] = { "cko1", "cko2", };
|
||||
static const char *lvds_sels[] = {
|
||||
|
||||
@@ -308,7 +308,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6);
|
||||
clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3);
|
||||
if (clk_on_imx6ul())
|
||||
clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3);
|
||||
else if (clk_on_imx6ull())
|
||||
clks[IMX6ULL_CLK_EPDC_PODF] = imx_clk_divider("epdc_podf", "epdc_pre_sel", base + 0x34, 12, 3);
|
||||
clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
|
||||
clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
|
||||
clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
|
||||
|
||||
@@ -51,20 +51,20 @@ static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
|
||||
|
||||
static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
|
||||
"pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",
|
||||
"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_usb_main_clk", };
|
||||
|
||||
static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
|
||||
"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", };
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", };
|
||||
|
||||
static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
|
||||
"pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",
|
||||
"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main_clk", };
|
||||
"pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", };
|
||||
|
||||
static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
|
||||
"pll_dram_533m_clk", "pll_enet_250m_clk",
|
||||
"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", };
|
||||
|
||||
static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
|
||||
@@ -74,8 +74,8 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
|
||||
|
||||
static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
|
||||
"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
|
||||
"pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div",
|
||||
"pll_video_main_clk", };
|
||||
"pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
|
||||
"pll_video_post_div", };
|
||||
|
||||
static const char *dram_phym_sel[] = { "pll_dram_main_clk",
|
||||
"dram_phym_alt_clk", };
|
||||
@@ -86,7 +86,7 @@ static const char *dram_sel[] = { "pll_dram_main_clk",
|
||||
static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
|
||||
"pll_sys_main_clk", "pll_enet_500m_clk",
|
||||
"pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",
|
||||
"pll_video_main_clk", };
|
||||
"pll_video_post_div", };
|
||||
|
||||
static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
|
||||
"pll_sys_main_clk", "pll_enet_500m_clk",
|
||||
@@ -108,62 +108,62 @@ static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
|
||||
static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
|
||||
"pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk",
|
||||
"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main_clk", };
|
||||
"pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",
|
||||
"pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk",
|
||||
"pll_sys_pfd2_270m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd2_270m_clk", "pll_video_post_div",
|
||||
"pll_usb_main_clk", };
|
||||
|
||||
static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",
|
||||
"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
|
||||
"pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };
|
||||
"pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
|
||||
|
||||
static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",
|
||||
"pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
|
||||
"pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };
|
||||
"pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
|
||||
|
||||
static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2",
|
||||
"pll_video_main_clk", "ext_clk_3", };
|
||||
"pll_video_post_div", "ext_clk_3", };
|
||||
|
||||
static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
|
||||
|
||||
static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
|
||||
|
||||
static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", };
|
||||
|
||||
static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
|
||||
"pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
|
||||
"pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", };
|
||||
|
||||
static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",
|
||||
"pll_enet_50m_clk", "pll_enet_25m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"ext_clk_4", };
|
||||
|
||||
static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
|
||||
"ext_clk_4", "pll_video_main_clk", };
|
||||
"ext_clk_4", "pll_video_post_div", };
|
||||
|
||||
static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",
|
||||
"pll_enet_50m_clk", "pll_enet_25m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"ext_clk_4", };
|
||||
|
||||
static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
|
||||
"ext_clk_4", "pll_video_main_clk", };
|
||||
"ext_clk_4", "pll_video_post_div", };
|
||||
|
||||
static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",
|
||||
"pll_enet_50m_clk", "pll_enet_125m_clk",
|
||||
"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_sys_pfd3_clk", };
|
||||
|
||||
static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
@@ -174,7 +174,7 @@ static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
static const char *nand_sel[] = { "osc", "pll_sys_main_clk",
|
||||
"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk",
|
||||
"pll_enet_500m_clk", "pll_enet_250m_clk",
|
||||
"pll_video_main_clk", };
|
||||
"pll_video_post_div", };
|
||||
|
||||
static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk",
|
||||
"pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk",
|
||||
@@ -204,22 +204,22 @@ static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
|
||||
static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_enet_50m_clk", "pll_dram_533m_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
|
||||
"pll_sys_pfd2_135m_clk", };
|
||||
|
||||
static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_enet_50m_clk", "pll_dram_533m_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
|
||||
"pll_sys_pfd2_135m_clk", };
|
||||
|
||||
static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_enet_50m_clk", "pll_dram_533m_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
|
||||
"pll_sys_pfd2_135m_clk", };
|
||||
|
||||
static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",
|
||||
"pll_enet_50m_clk", "pll_dram_533m_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
|
||||
"pll_sys_pfd2_135m_clk", };
|
||||
|
||||
static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
|
||||
@@ -279,27 +279,27 @@ static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk",
|
||||
|
||||
static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
|
||||
"ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };
|
||||
"ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
|
||||
|
||||
static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_dram_533m_clk",
|
||||
@@ -308,23 +308,23 @@ static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
|
||||
static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_dram_533m_clk",
|
||||
"pll_usb_main_clk", "pll_video_main_clk", "pll_enet_125m_clk",
|
||||
"pll_usb_main_clk", "pll_video_post_div", "pll_enet_125m_clk",
|
||||
"pll_sys_pfd7_clk", };
|
||||
|
||||
static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
|
||||
"ref_1m_clk", "pll_audio_post_div", "ext_clk_1", };
|
||||
|
||||
static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
|
||||
"ref_1m_clk", "pll_audio_post_div", "ext_clk_2", };
|
||||
|
||||
static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
|
||||
"ref_1m_clk", "pll_audio_post_div", "ext_clk_3", };
|
||||
|
||||
static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
|
||||
"ref_1m_clk", "pll_audio_post_div", "ext_clk_4", };
|
||||
|
||||
static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
@@ -339,12 +339,12 @@ static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
|
||||
static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_dram_533m_clk",
|
||||
"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_usb_main_clk", };
|
||||
|
||||
static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
|
||||
"pll_sys_main_120m_clk", "pll_dram_533m_clk",
|
||||
"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",
|
||||
"pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
|
||||
"pll_usb_main_clk", };
|
||||
|
||||
static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
|
||||
@@ -358,13 +358,13 @@ static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
|
||||
|
||||
static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
|
||||
"pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "ckil", };
|
||||
"pll_audio_post_div", "pll_video_post_div", "ckil", };
|
||||
|
||||
static const char *lvds1_sel[] = { "pll_arm_main_clk",
|
||||
"pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
|
||||
"pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
|
||||
"pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",
|
||||
"pll_audio_post_div", "pll_video_main_clk", "pll_enet_500m_clk",
|
||||
"pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk",
|
||||
"pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",
|
||||
"pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",
|
||||
"pll_dram_main_clk", };
|
||||
@@ -433,23 +433,22 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
|
||||
clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
|
||||
|
||||
clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
|
||||
|
||||
clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
|
||||
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13);
|
||||
clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
|
||||
clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
|
||||
clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
|
||||
clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
|
||||
|
||||
clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock);
|
||||
clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
|
||||
clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clks[IMX7D_PLL_VIDEO_TEST_DIV] = clk_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_clk",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock);
|
||||
clks[IMX7D_PLL_VIDEO_POST_DIV] = clk_register_divider_table(NULL, "pll_video_post_div", "pll_video_test_div",
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
|
||||
clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0);
|
||||
clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1);
|
||||
@@ -797,7 +796,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
|
||||
clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
|
||||
clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
|
||||
clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
|
||||
clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
|
||||
clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
|
||||
clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
|
||||
clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
|
||||
@@ -863,6 +862,9 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
|
||||
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
|
||||
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
|
||||
clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0);
|
||||
clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0);
|
||||
clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0);
|
||||
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
|
||||
|
||||
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
|
||||
@@ -882,12 +884,23 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clks[clks_init_on[i]]);
|
||||
|
||||
clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
|
||||
clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
|
||||
|
||||
/* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
|
||||
clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
|
||||
|
||||
/* set uart module clock's parent clock source that must be great then 80MHz */
|
||||
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
|
||||
|
||||
/* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
|
||||
clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
|
||||
clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
}
|
||||
|
||||
@@ -182,8 +182,12 @@ static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
u32 dp_op, dp_mfd, dp_mfn;
|
||||
int ret;
|
||||
|
||||
ret = __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
__clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
|
||||
return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
|
||||
dp_op, dp_mfd, dp_mfn);
|
||||
}
|
||||
|
||||
@@ -123,6 +123,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
|
||||
shift, 0, &imx_ccm_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift, unsigned long flags)
|
||||
{
|
||||
return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
|
||||
shift, 0, &imx_ccm_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift)
|
||||
{
|
||||
@@ -137,6 +144,13 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
|
||||
shift, 0x3, 0, &imx_ccm_lock, NULL);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift, unsigned long flags)
|
||||
{
|
||||
return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
|
||||
shift, 0x3, 0, &imx_ccm_lock, NULL);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate2_shared(const char *name,
|
||||
const char *parent, void __iomem *reg, u8 shift,
|
||||
unsigned int *share_count)
|
||||
|
||||
Reference in New Issue
Block a user