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MIPS: Octeon: Implement delays with cycle counter.

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Power throttling make deterministic delay loops impossible.
Re-implement delays using the cycle counter.  This also allows us to
get rid of the code that calculates loops per jiffy.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1317/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
2010-06-01 13:18:15 -07:00
committed by Ralf Baechle
parent e6b78c4f22
commit ca148125e6
4 changed files with 58 additions and 13 deletions
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11
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
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@@ -61,22 +61,11 @@
#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
#define ARCH_HAS_READ_CURRENT_TIMER 1
#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1
#define spin_lock_prefetch(x) prefetch(x)
#define PREFETCH_STRIDE 128
static inline int read_current_timer(unsigned long *result)
{
asm volatile ("rdhwr %0,$31\n"
#ifndef CONFIG_64BIT
"\tsll %0, 0"
#endif
: "=r" (*result));
return 0;
}
#ifdef __OCTEON__
/*
* All gcc versions that have OCTEON support define __OCTEON__ and have the