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Merge tag 'arc-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

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Pull ARC updates from Vineet Gupta:

 - more changes for HS48 cores: supporting MMUv5, detecting new
   micro-arch gizmos

 - axs10x platform wiring up reset driver merged in this cycle

 - ARC perf driver optimizations

* tag 'arc-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: perf: avoid vmalloc backed mmap
  ARCv2: perf: optimize given that num counters <= 32
  ARCv2: perf: tweak overflow interrupt
  ARC: [plat-axs10x] DTS: Add reset controller node to manage ethernet reset
  ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop Buffer
  ARCv2: Accomodate HS48 MMUv5 by relaxing MMU ver checking
  ARC: [plat-axs10x] auto-select AXS101 or AXS103 given the  ISA config
This commit is contained in:
Linus Torvalds
2017-11-25 08:21:54 -10:00
parent 5e2fda4776 82385732b1
commit ca122fe376
8 changed files with 135 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
arch/arc/include/asm/arcregs.h
View File

@@ -11,12 +11,14 @@
/* Build Configuration Registers */
#define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
#define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
#define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
#define ARC_REG_CRC_BCR 0x62
#define ARC_REG_VECBASE_BCR 0x68
#define ARC_REG_PERIBASE_BCR 0x69
#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
#define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
#define ARC_REG_SLC_BCR 0xce
#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
@@ -32,11 +34,14 @@
#define ARC_REG_D_UNCACH_BCR 0x6A
#define ARC_REG_BPU_BCR 0xc0
#define ARC_REG_ISA_CFG_BCR 0xc1
#define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
#define ARC_REG_RTT_BCR 0xF2
#define ARC_REG_IRQ_BCR 0xF3
#define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
#define ARC_REG_SMART_BCR 0xFF
#define ARC_REG_CLUSTER_BCR 0xcf
#define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
#define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
/* Common for ARCompact and ARCv2 status register */
#define ARC_REG_STATUS32 0x0A
@@ -229,6 +234,32 @@ struct bcr_bpu_arcv2 {
#endif
};
/* Error Protection Build: ECC/Parity */
struct bcr_erp {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
#else
unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
#endif
};
/* Error Protection Control */
struct ctl_erp {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
#else
unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
#endif
};
struct bcr_lpb {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int pad:16, entries:8, ver:8;
#else
unsigned int ver:8, entries:8, pad:16;
#endif
};
struct bcr_generic {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int info:24, ver:8;
@@ -270,7 +301,7 @@ struct cpuinfo_arc {
struct cpuinfo_arc_ccm iccm, dccm;
struct {
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
debug:1, ap:1, smart:1, rtt:1, pad3:4,
timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
} extn;