drm/radeon/kms: fix bandwidth computation on avivo hardware
Fix bandwidth computation and crtc priority in memory controller so that crtc memory request are fullfill in time to avoid display artifact. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Jerome Glisse
committed by
Dave Airlie
Dave Airlie
parent
e024e11070
commit
c93bb85b5c
@@ -154,7 +154,6 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
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if (mode->hdisplay < native_mode->panel_xres ||
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mode->vdisplay < native_mode->panel_yres) {
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radeon_encoder->flags |= RADEON_USE_RMX;
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if (ASIC_IS_AVIVO(rdev)) {
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adjusted_mode->hdisplay = native_mode->panel_xres;
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adjusted_mode->vdisplay = native_mode->panel_yres;
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@@ -197,15 +196,13 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
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}
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}
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static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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radeon_encoder->flags &= ~RADEON_USE_RMX;
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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if (radeon_encoder->rmx_type != RMX_OFF)
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@@ -808,234 +805,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
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}
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static void atom_rv515_force_tv_scaler(struct radeon_device *rdev)
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{
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WREG32(0x659C, 0x0);
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WREG32(0x6594, 0x705);
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WREG32(0x65A4, 0x10001);
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WREG32(0x65D8, 0x0);
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WREG32(0x65B0, 0x0);
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WREG32(0x65C0, 0x0);
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WREG32(0x65D4, 0x0);
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WREG32(0x6578, 0x0);
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WREG32(0x657C, 0x841880A8);
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WREG32(0x6578, 0x1);
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WREG32(0x657C, 0x84208680);
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WREG32(0x6578, 0x2);
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WREG32(0x657C, 0xBFF880B0);
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WREG32(0x6578, 0x100);
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WREG32(0x657C, 0x83D88088);
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WREG32(0x6578, 0x101);
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WREG32(0x657C, 0x84608680);
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WREG32(0x6578, 0x102);
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WREG32(0x657C, 0xBFF080D0);
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WREG32(0x6578, 0x200);
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WREG32(0x657C, 0x83988068);
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WREG32(0x6578, 0x201);
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WREG32(0x657C, 0x84A08680);
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WREG32(0x6578, 0x202);
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WREG32(0x657C, 0xBFF080F8);
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WREG32(0x6578, 0x300);
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WREG32(0x657C, 0x83588058);
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WREG32(0x6578, 0x301);
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WREG32(0x657C, 0x84E08660);
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WREG32(0x6578, 0x302);
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WREG32(0x657C, 0xBFF88120);
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WREG32(0x6578, 0x400);
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WREG32(0x657C, 0x83188040);
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WREG32(0x6578, 0x401);
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WREG32(0x657C, 0x85008660);
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WREG32(0x6578, 0x402);
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WREG32(0x657C, 0xBFF88150);
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WREG32(0x6578, 0x500);
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WREG32(0x657C, 0x82D88030);
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WREG32(0x6578, 0x501);
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WREG32(0x657C, 0x85408640);
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WREG32(0x6578, 0x502);
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WREG32(0x657C, 0xBFF88180);
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WREG32(0x6578, 0x600);
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WREG32(0x657C, 0x82A08018);
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WREG32(0x6578, 0x601);
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WREG32(0x657C, 0x85808620);
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WREG32(0x6578, 0x602);
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WREG32(0x657C, 0xBFF081B8);
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WREG32(0x6578, 0x700);
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WREG32(0x657C, 0x82608010);
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WREG32(0x6578, 0x701);
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WREG32(0x657C, 0x85A08600);
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WREG32(0x6578, 0x702);
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WREG32(0x657C, 0x800081F0);
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WREG32(0x6578, 0x800);
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WREG32(0x657C, 0x8228BFF8);
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WREG32(0x6578, 0x801);
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WREG32(0x657C, 0x85E085E0);
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WREG32(0x6578, 0x802);
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WREG32(0x657C, 0xBFF88228);
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WREG32(0x6578, 0x10000);
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WREG32(0x657C, 0x82A8BF00);
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WREG32(0x6578, 0x10001);
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WREG32(0x657C, 0x82A08CC0);
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WREG32(0x6578, 0x10002);
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WREG32(0x657C, 0x8008BEF8);
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WREG32(0x6578, 0x10100);
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WREG32(0x657C, 0x81F0BF28);
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WREG32(0x6578, 0x10101);
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WREG32(0x657C, 0x83608CA0);
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WREG32(0x6578, 0x10102);
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WREG32(0x657C, 0x8018BED0);
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WREG32(0x6578, 0x10200);
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WREG32(0x657C, 0x8148BF38);
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WREG32(0x6578, 0x10201);
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WREG32(0x657C, 0x84408C80);
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WREG32(0x6578, 0x10202);
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WREG32(0x657C, 0x8008BEB8);
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WREG32(0x6578, 0x10300);
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WREG32(0x657C, 0x80B0BF78);
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WREG32(0x6578, 0x10301);
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WREG32(0x657C, 0x85008C20);
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WREG32(0x6578, 0x10302);
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WREG32(0x657C, 0x8020BEA0);
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WREG32(0x6578, 0x10400);
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WREG32(0x657C, 0x8028BF90);
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WREG32(0x6578, 0x10401);
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WREG32(0x657C, 0x85E08BC0);
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WREG32(0x6578, 0x10402);
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WREG32(0x657C, 0x8018BE90);
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WREG32(0x6578, 0x10500);
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WREG32(0x657C, 0xBFB8BFB0);
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WREG32(0x6578, 0x10501);
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WREG32(0x657C, 0x86C08B40);
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WREG32(0x6578, 0x10502);
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WREG32(0x657C, 0x8010BE90);
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WREG32(0x6578, 0x10600);
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WREG32(0x657C, 0xBF58BFC8);
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WREG32(0x6578, 0x10601);
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WREG32(0x657C, 0x87A08AA0);
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WREG32(0x6578, 0x10602);
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WREG32(0x657C, 0x8010BE98);
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WREG32(0x6578, 0x10700);
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WREG32(0x657C, 0xBF10BFF0);
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WREG32(0x6578, 0x10701);
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WREG32(0x657C, 0x886089E0);
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WREG32(0x6578, 0x10702);
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WREG32(0x657C, 0x8018BEB0);
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WREG32(0x6578, 0x10800);
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WREG32(0x657C, 0xBED8BFE8);
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WREG32(0x6578, 0x10801);
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WREG32(0x657C, 0x89408940);
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WREG32(0x6578, 0x10802);
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WREG32(0x657C, 0xBFE8BED8);
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WREG32(0x6578, 0x20000);
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WREG32(0x657C, 0x80008000);
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WREG32(0x6578, 0x20001);
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WREG32(0x657C, 0x90008000);
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WREG32(0x6578, 0x20002);
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WREG32(0x657C, 0x80008000);
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WREG32(0x6578, 0x20003);
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WREG32(0x657C, 0x80008000);
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WREG32(0x6578, 0x20100);
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WREG32(0x657C, 0x80108000);
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WREG32(0x6578, 0x20101);
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WREG32(0x657C, 0x8FE0BF70);
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WREG32(0x6578, 0x20102);
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WREG32(0x657C, 0xBFE880C0);
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WREG32(0x6578, 0x20103);
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WREG32(0x657C, 0x80008000);
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WREG32(0x6578, 0x20200);
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WREG32(0x657C, 0x8018BFF8);
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WREG32(0x6578, 0x20201);
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WREG32(0x657C, 0x8F80BF08);
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WREG32(0x6578, 0x20202);
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WREG32(0x657C, 0xBFD081A0);
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WREG32(0x6578, 0x20203);
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WREG32(0x657C, 0xBFF88000);
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WREG32(0x6578, 0x20300);
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WREG32(0x657C, 0x80188000);
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WREG32(0x6578, 0x20301);
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WREG32(0x657C, 0x8EE0BEC0);
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WREG32(0x6578, 0x20302);
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WREG32(0x657C, 0xBFB082A0);
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WREG32(0x6578, 0x20303);
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WREG32(0x657C, 0x80008000);
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WREG32(0x6578, 0x20400);
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WREG32(0x657C, 0x80188000);
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WREG32(0x6578, 0x20401);
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WREG32(0x657C, 0x8E00BEA0);
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WREG32(0x6578, 0x20402);
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WREG32(0x657C, 0xBF8883C0);
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WREG32(0x6578, 0x20403);
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WREG32(0x657C, 0x80008000);
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WREG32(0x6578, 0x20500);
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WREG32(0x657C, 0x80188000);
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WREG32(0x6578, 0x20501);
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WREG32(0x657C, 0x8D00BE90);
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WREG32(0x6578, 0x20502);
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WREG32(0x657C, 0xBF588500);
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WREG32(0x6578, 0x20503);
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WREG32(0x657C, 0x80008008);
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WREG32(0x6578, 0x20600);
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WREG32(0x657C, 0x80188000);
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WREG32(0x6578, 0x20601);
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WREG32(0x657C, 0x8BC0BE98);
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WREG32(0x6578, 0x20602);
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WREG32(0x657C, 0xBF308660);
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WREG32(0x6578, 0x20603);
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WREG32(0x657C, 0x80008008);
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WREG32(0x6578, 0x20700);
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WREG32(0x657C, 0x80108000);
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WREG32(0x6578, 0x20701);
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WREG32(0x657C, 0x8A80BEB0);
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WREG32(0x6578, 0x20702);
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WREG32(0x657C, 0xBF0087C0);
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WREG32(0x6578, 0x20703);
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WREG32(0x657C, 0x80008008);
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WREG32(0x6578, 0x20800);
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WREG32(0x657C, 0x80108000);
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WREG32(0x6578, 0x20801);
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WREG32(0x657C, 0x8920BED0);
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WREG32(0x6578, 0x20802);
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WREG32(0x657C, 0xBED08920);
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WREG32(0x6578, 0x20803);
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WREG32(0x657C, 0x80008010);
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WREG32(0x6578, 0x30000);
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WREG32(0x657C, 0x90008000);
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WREG32(0x6578, 0x30001);
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WREG32(0x657C, 0x80008000);
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WREG32(0x6578, 0x30100);
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WREG32(0x657C, 0x8FE0BF90);
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WREG32(0x6578, 0x30101);
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WREG32(0x657C, 0xBFF880A0);
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WREG32(0x6578, 0x30200);
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WREG32(0x657C, 0x8F60BF40);
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WREG32(0x6578, 0x30201);
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WREG32(0x657C, 0xBFE88180);
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WREG32(0x6578, 0x30300);
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WREG32(0x657C, 0x8EC0BF00);
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WREG32(0x6578, 0x30301);
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WREG32(0x657C, 0xBFC88280);
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WREG32(0x6578, 0x30400);
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WREG32(0x657C, 0x8DE0BEE0);
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WREG32(0x6578, 0x30401);
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WREG32(0x657C, 0xBFA083A0);
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WREG32(0x6578, 0x30500);
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WREG32(0x657C, 0x8CE0BED0);
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WREG32(0x6578, 0x30501);
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WREG32(0x657C, 0xBF7884E0);
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WREG32(0x6578, 0x30600);
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WREG32(0x657C, 0x8BA0BED8);
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WREG32(0x6578, 0x30601);
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WREG32(0x657C, 0xBF508640);
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WREG32(0x6578, 0x30700);
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WREG32(0x657C, 0x8A60BEE8);
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WREG32(0x6578, 0x30701);
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WREG32(0x657C, 0xBF2087A0);
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WREG32(0x6578, 0x30800);
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WREG32(0x657C, 0x8900BF00);
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WREG32(0x6578, 0x30801);
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WREG32(0x657C, 0xBF008900);
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}
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static void
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atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
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{
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@@ -1073,129 +842,6 @@ atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
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WREG32(reg, temp);
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}
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static void
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atombios_overscan_setup(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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SET_CRTC_OVERSCAN_PS_ALLOCATION args;
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int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
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memset(&args, 0, sizeof(args));
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args.usOverscanRight = 0;
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args.usOverscanLeft = 0;
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args.usOverscanBottom = 0;
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args.usOverscanTop = 0;
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args.ucCRTC = radeon_crtc->crtc_id;
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if (radeon_encoder->flags & RADEON_USE_RMX) {
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if (radeon_encoder->rmx_type == RMX_FULL) {
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args.usOverscanRight = 0;
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args.usOverscanLeft = 0;
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args.usOverscanBottom = 0;
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args.usOverscanTop = 0;
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} else if (radeon_encoder->rmx_type == RMX_CENTER) {
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args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
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args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
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args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
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args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
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} else if (radeon_encoder->rmx_type == RMX_ASPECT) {
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int a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
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int a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
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if (a1 > a2) {
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args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
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args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
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} else if (a2 > a1) {
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args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
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args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
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}
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}
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}
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void
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atombios_scaler_setup(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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ENABLE_SCALER_PS_ALLOCATION args;
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int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
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/* fixme - fill in enc_priv for atom dac */
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enum radeon_tv_std tv_std = TV_STD_NTSC;
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if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
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return;
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memset(&args, 0, sizeof(args));
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args.ucScaler = radeon_crtc->crtc_id;
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if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
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switch (tv_std) {
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case TV_STD_NTSC:
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default:
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args.ucTVStandard = ATOM_TV_NTSC;
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break;
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case TV_STD_PAL:
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args.ucTVStandard = ATOM_TV_PAL;
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break;
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case TV_STD_PAL_M:
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args.ucTVStandard = ATOM_TV_PALM;
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break;
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case TV_STD_PAL_60:
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args.ucTVStandard = ATOM_TV_PAL60;
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break;
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case TV_STD_NTSC_J:
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args.ucTVStandard = ATOM_TV_NTSCJ;
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break;
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case TV_STD_SCART_PAL:
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args.ucTVStandard = ATOM_TV_PAL; /* ??? */
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break;
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case TV_STD_SECAM:
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args.ucTVStandard = ATOM_TV_SECAM;
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break;
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case TV_STD_PAL_CN:
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args.ucTVStandard = ATOM_TV_PALCN;
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break;
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}
|
||||
args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
|
||||
} else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) {
|
||||
args.ucTVStandard = ATOM_TV_CV;
|
||||
args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
|
||||
} else if (radeon_encoder->flags & RADEON_USE_RMX) {
|
||||
if (radeon_encoder->rmx_type == RMX_FULL)
|
||||
args.ucEnable = ATOM_SCALER_EXPANSION;
|
||||
else if (radeon_encoder->rmx_type == RMX_CENTER)
|
||||
args.ucEnable = ATOM_SCALER_CENTER;
|
||||
else if (radeon_encoder->rmx_type == RMX_ASPECT)
|
||||
args.ucEnable = ATOM_SCALER_EXPANSION;
|
||||
} else {
|
||||
if (ASIC_IS_AVIVO(rdev))
|
||||
args.ucEnable = ATOM_SCALER_DISABLE;
|
||||
else
|
||||
args.ucEnable = ATOM_SCALER_CENTER;
|
||||
}
|
||||
|
||||
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
|
||||
|
||||
if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)
|
||||
&& rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) {
|
||||
atom_rv515_force_tv_scaler(rdev);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void
|
||||
radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
@@ -1448,8 +1094,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
|
||||
radeon_encoder->pixel_clock = adjusted_mode->clock;
|
||||
|
||||
radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
|
||||
atombios_overscan_setup(encoder, mode, adjusted_mode);
|
||||
atombios_scaler_setup(encoder);
|
||||
atombios_set_encoder_crtc_source(encoder);
|
||||
|
||||
if (ASIC_IS_AVIVO(rdev)) {
|
||||
@@ -1667,6 +1311,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
|
||||
|
||||
radeon_encoder->encoder_id = encoder_id;
|
||||
radeon_encoder->devices = supported_device;
|
||||
radeon_encoder->rmx_type = RMX_OFF;
|
||||
|
||||
switch (radeon_encoder->encoder_id) {
|
||||
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
|
||||
@@ -1700,14 +1345,8 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
|
||||
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
|
||||
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
|
||||
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
|
||||
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
|
||||
radeon_encoder->rmx_type = RMX_FULL;
|
||||
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
|
||||
radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
|
||||
} else {
|
||||
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
|
||||
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
|
||||
}
|
||||
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
|
||||
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
|
||||
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
|
||||
break;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user