xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC late DT updates from Arnd Bergmann:
 "These updates have been kept in a separate branch mostly because they
  rely on updates to the respective clk drivers to keep the shared
  header files in sync.

   - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an
     automotive SoC similar to the ⅹ8a7795 chip we already support, but
     the dts changes rely on a clock driver change that has been merged
     for v4.9 through the clk tree.

   - The Amlogic meson-gxbb (S905) platform gains support for a few
     drivers merged through our tree, in particular the network and usb
     driver changes are required and included here, and also the clk
     tree changes.

   - The Allwinner platforms have seen a large-scale change to their clk
     drivers and the dts file updates must come after that. This
     includes the newly added Nextthing GR8 platform, which is derived
     from sun5i/A13.

   - Some integrator (arm32) changes rely on clk driver changes.

   - A single patch for lpc32xx has no such dependency but wasn't added
     until just before the merge window"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  ARM: dts: lpc32xx: add device node for IRAM on-chip memory
  ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03
  ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board
  ARM: dts: sun8i: add pinmux for UART1 at PG
  dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
  dts: sun8i-h3: add pinmux definitions for I2C0-2
  dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards
  dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux
  dts: sun8i-h3: add pinmux definitions for UART2-3
  ARM: dts: sun9i: a80-optimus: Disable EHCI1
  ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused
  ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused
  ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h
  ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes
  ...
This commit is contained in:
Linus Torvalds
2016-10-07 21:34:49 -07:00
parent a439f8f287 8185041f5f
commit c913fc4146
51 changed files with 4157 additions and 874 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@@ -745,6 +745,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-pcduino2.dtb \
sun4i-a10-pov-protab2-ips9.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
ntc-gr8-evb.dtb \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
sun5i-a10s-mk802.dtb \

51
arch/arm/boot/dts/integratorap.dts
View File

@@ -19,7 +19,7 @@
bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
};
/* 24 MHz chrystal on the core module */
/* 24 MHz chrystal on the Integrator/AP development board */
xtal24mhz: xtal24mhz@24M {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -39,6 +39,34 @@
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
clocks = <&xtal24mhz>;
};
core-module@10000000 {
/* 24 MHz chrystal on the core module */
cm24mhz: cm24mhz@24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
/* Oscillator on the core module, clocks the CPU core */
cmosc: cmosc@24M {
compatible = "arm,syscon-icst525-integratorap-cm";
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x08>;
clocks = <&cm24mhz>;
};
/* Auxilary oscillator on the core module, 32.369MHz at boot */
auxosc: auxosc@24M {
compatible = "arm,syscon-icst525";
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x1c>;
clocks = <&cm24mhz>;
};
};
syscon {
@@ -47,6 +75,27 @@
interrupt-parent = <&pic>;
/* These are the logical module IRQs */
interrupts = <9>, <10>, <11>, <12>;
/*
* SYSCLK clocks PCIv3 bridge, system controller and the
* logic modules.
*/
sysclk: apsys@24M {
compatible = "arm,syscon-icst525-integratorap-sys";
#clock-cells = <0>;
lock-offset = <0x1c>;
vco-offset = <0x04>;
clocks = <&xtal24mhz>;
};
/* One-bit control for the PCI bus clock (33 or 25 MHz) */
pciclk: pciclk@24M {
compatible = "arm,syscon-icst525-integratorap-pci";
#clock-cells = <0>;
lock-offset = <0x1c>;
vco-offset = <0x04>;
clocks = <&xtal24mhz>;
};
};
timer0: timer@13000000 {

74
arch/arm/boot/dts/integratorcp.dts
View File

@@ -58,20 +58,37 @@
core-module@10000000 {
/* 24 MHz chrystal on the core module */
xtal24mhz: xtal24mhz@24M {
cm24mhz: cm24mhz@24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
/*
* External oscillator on the core module, usually used
* to drive video circuitry. Driven from the 24MHz clock.
*/
auxosc: cm_aux_osc@25M {
/* Oscillator on the core module, clocks the CPU core */
cmcore: cmosc@24M {
compatible = "arm,syscon-icst525-integratorcp-cm-core";
#clock-cells = <0>;
compatible = "arm,integrator-cm-auxosc";
clocks = <&xtal24mhz>;
lock-offset = <0x14>;
vco-offset = <0x08>;
clocks = <&cm24mhz>;
};
/* Oscillator on the core module, clocks the memory bus */
cmmem: cmosc@24M {
compatible = "arm,syscon-icst525-integratorcp-cm-mem";
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x08>;
clocks = <&cm24mhz>;
};
/* Auxilary oscillator on the core module, clocks the CLCD */
auxosc: auxosc@24M {
compatible = "arm,syscon-icst525";
#clock-cells = <0>;
lock-offset = <0x14>;
vco-offset = <0x1c>;
clocks = <&cm24mhz>;
};
/* The KMI clock is the 24 MHz oscillator divided to 8MHz */
@@ -80,7 +97,7 @@
compatible = "fixed-factor-clock";
clock-div = <3>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
clocks = <&cm24mhz>;
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
@@ -89,7 +106,7 @@
compatible = "fixed-factor-clock";
clock-div = <24>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
clocks = <&cm24mhz>;
};
};
@@ -209,7 +226,42 @@
reg = <0xC0000000 0x1000>;
interrupts = <22>;
clocks = <&auxosc>, <&pclk>;
clock-names = "clcd", "apb_pclk";
clock-names = "clcdclk", "apb_pclk";
port {
/*
* The VGA connected is implemented with a
* THS8134A triple DAC that can be run in 24bit
* or 16bit RGB mode.
*/
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
};
};
panel {
compatible = "panel-dpi";
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
/* Standard 640x480 VGA timings */
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <48>;
hfront-porch = <16>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <33>;
vfront-porch = <10>;
vsync-len = <2>;
};
};
};
};
};

12
arch/arm/boot/dts/lpc32xx.dtsi
View File

@@ -51,9 +51,19 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x20000000 0x20000000 0x30000000>,
ranges = <0x00000000 0x00000000 0x10000000>,
<0x20000000 0x20000000 0x30000000>,
<0xe0000000 0xe0000000 0x04000000>;
iram: sram@08000000 {
compatible = "mmio-sram";
reg = <0x08000000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x08000000 0x20000>;
};
/*
* Enable either SLC or MLC
*/

342
arch/arm/boot/dts/ntc-gr8-evb.dts Normal file
View File

@@ -0,0 +1,342 @@
/*
* Copyright 2016 Free Electrons
* Copyright 2016 NextThing Co
*
* Mylène Josserand <mylene.josserand@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "ntc-gr8.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "NextThing GR8-EVB";
compatible = "nextthing,gr8-evb", "nextthing,gr8";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
serial0 = &uart1;
serial1 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 10000 0>;
enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
};
};
&be0 {
status = "okay";
};
&codec {
status = "okay";
};
&ehci0 {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
/*
* The interrupt is routed through the "External Fast
* Interrupt Request" pin (ball G13 of the module)
* directly to the main interrupt controller, without
* any other controller interfering.
*/
interrupts = <0>;
};
};
#include "axp209.dtsi"
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
wm8978: codec@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8978";
reg = <0x1a>;
};
pcf8563: rtc@51 {
compatible = "phg,pcf8563";
reg = <0x51>;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&i2s0 {
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>;
status = "okay";
};
&ir0 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_rx_pins_a>;
status = "okay";
};
&lradc {
vref-supply = <&reg_ldo2>;
status = "okay";
button@190 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <190000>;
};
button@390 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <390000>;
};
button@600 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <600000>;
};
button@800 {
label = "Search";
linux,code = <KEY_SEARCH>;
channel = <0>;
voltage = <800000>;
};
button@980 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
voltage = <980000>;
};
button@1180 {
label = "Esc";
linux,code = <KEY_ESC>;
channel = <0>;
voltage = <1180000>;
};
button@1400 {
label = "Enter";
linux,code = <KEY_ENTER>;
channel = <0>;
voltage = <1400000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
cd-inverted;
status = "okay";
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
/* MLC Support sucks for now */
status = "disabled";
};
&ohci0 {
status = "okay";
};
&otg_sram {
status = "okay";
};
&pio {
mmc0_cd_pin_gr8_evb: mmc0-cd-pin@0 {
allwinner,pins = "PG0";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_id_pin_gr8_evb: usb0-id-pin@0 {
allwinner,pins = "PG2";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb0_vbus_det_pin_gr8_evb: usb0-vbus-det-pin@0 {
allwinner,pins = "PG1";
allwinner,function = "gpio_in";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
usb1_vbus_pin_gr8_evb: usb1-vbus-pin@0 {
allwinner,pins = "PG13";
allwinner,function = "gpio_out";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins_a>;
status = "okay";
};
&reg_dcdc2 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
regulator-always-on;
};
&reg_dcdc3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vdd-sys";
regulator-always-on;
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
regulator-name = "avcc";
regulator-always-on;
};
&reg_usb1_vbus {
pinctrl-0 = <&usb1_vbus_pin_gr8_evb>;
gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&rtp {
allwinner,ts-attached;
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pins_a>;
status = "okay";
};
&tve0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
status = "okay";
};
&usb_otg {
/*
* The GR8-EVB has a somewhat interesting design. There's a
* pin supposed to control VBUS, an ID pin, a VBUS detect pin,
* so everything should work just fine.
*
* Except that the pin supposed to control VBUS is not
* connected to any controllable output, neither to the SoC
* through a GPIO or to the PMIC, and it is pulled down,
* meaning that we will never be able to enable VBUS on this
* board.
*/
dr_mode = "otg";
status = "okay";
};
&usb_power_supply {
status = "okay";
};
&usbphy {
pinctrl-names = "default";
pinctrl-0 = <&usb0_id_pin_gr8_evb>, <&usb0_vbus_det_pin_gr8_evb>;
usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

1087
arch/arm/boot/dts/ntc-gr8.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

424
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@@ -47,7 +47,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/clock/sun6i-a31-ccu.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -65,7 +67,10 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll6 0>;
clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
<&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
<&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
<&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
status = "disabled";
};
@@ -73,7 +78,9 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <&pll6 0>;
clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
<&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
<&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
status = "disabled";
};
};
@@ -97,7 +104,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clocks = <&cpu>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHz uV */
@@ -192,235 +199,6 @@
clock-output-names = "osc32k";
};
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
pll6: clk@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6", "pll6x2";
};
cpu: cpu@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20050 0x4>;
/*
* PLL1 is listed twice here.
* While it looks suspicious, it's actually documented
* that way both in the datasheet and in the code from
* Allwinner.
*/
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
clock-output-names = "cpu";
};
axi: axi@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20050 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
};
ahb1: ahb1@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1";
/*
* Clock AHB1 from PLL6, instead of CPU/AXI which
* has rate changes due to cpufreq. Also the DMA
* controller requires AHB1 clocked from PLL6.
*/
assigned-clocks = <&ahb1>;
assigned-clock-parents = <&pll6 0>;
};
ahb1_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
clock-indices = <1>, <5>,
<6>, <8>, <9>,
<10>, <11>, <12>,
<13>, <14>,
<17>, <18>, <19>,
<20>, <21>, <22>,
<23>, <24>, <26>,
<27>, <29>,
<30>, <31>, <32>,
<36>, <37>, <40>,
<43>, <44>, <45>,
<46>, <47>, <50>,
<52>, <55>, <56>,
<57>, <58>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
"ahb1_nand0", "ahb1_sdram",
"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
"ahb1_ehci1", "ahb1_ohci0",
"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
"ahb1_drc0", "ahb1_drc1";
};
apb1: apb1@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1>;
clock-output-names = "apb1";
};
apb1_gates: clk@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
clock-indices = <0>, <4>,
<5>, <12>,
<13>;
clock-output-names = "apb1_codec", "apb1_digital_mic",
"apb1_pio", "apb1_daudio0",
"apb1_daudio1";
};
apb2: clk@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
clock-output-names = "apb2";
};
apb2_gates: clk@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
clock-indices = <0>, <1>,
<2>, <3>, <16>,
<17>, <18>, <19>,
<20>, <21>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_i2c3",
"apb2_uart0", "apb2_uart1",
"apb2_uart2", "apb2_uart3",
"apb2_uart4", "apb2_uart5";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
mmc3_clk: clk@01c20094 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20094 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc3",
"mmc3_output",
"mmc3_sample";
};
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "ss";
};
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a0 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "spi0";
};
spi1_clk: clk@01c200a4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a4 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "spi1";
};
spi2_clk: clk@01c200a8 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a8 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "spi2";
};
spi3_clk: clk@01c200ac {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200ac 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "spi3";
};
usb_clk: clk@01c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
clock-indices = <8>, <9>, <10>,
<16>, <17>,
<18>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
"usb_ohci0", "usb_ohci1",
"usb_ohci2";
};
/*
* The following two are dummy clocks, placeholders
* used in the gmac_tx clock. The gmac driver will
@@ -463,23 +241,23 @@
compatible = "allwinner,sun6i-a31-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 6>;
resets = <&ahb1_rst 6>;
clocks = <&ccu CLK_AHB1_DMA>;
resets = <&ccu RST_AHB1_DMA>;
#dma-cells = <1>;
};
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb1_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clocks = <&ccu CLK_AHB1_MMC0>,
<&ccu CLK_MMC0>,
<&ccu CLK_MMC0_OUTPUT>,
<&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 8>;
resets = <&ccu RST_AHB1_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -490,15 +268,15 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ahb1_gates 9>,
<&mmc1_clk 0>,
<&mmc1_clk 1>,
<&mmc1_clk 2>;
clocks = <&ccu CLK_AHB1_MMC1>,
<&ccu CLK_MMC1>,
<&ccu CLK_MMC1_OUTPUT>,
<&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 9>;
resets = <&ccu RST_AHB1_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -509,15 +287,15 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb1_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clocks = <&ccu CLK_AHB1_MMC2>,
<&ccu CLK_MMC2>,
<&ccu CLK_MMC2_OUTPUT>,
<&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 10>;
resets = <&ccu RST_AHB1_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -528,15 +306,15 @@
mmc3: mmc@01c12000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c12000 0x1000>;
clocks = <&ahb1_gates 11>,
<&mmc3_clk 0>,
<&mmc3_clk 1>,
<&mmc3_clk 2>;
clocks = <&ccu CLK_AHB1_MMC3>,
<&ccu CLK_MMC3>,
<&ccu CLK_MMC3_OUTPUT>,
<&ccu CLK_MMC3_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 11>;
resets = <&ccu RST_AHB1_MMC3>;
reset-names = "ahb";
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -547,8 +325,8 @@
usb_otg: usb@01c19000 {
compatible = "allwinner,sun6i-a31-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ahb1_gates 24>;
resets = <&ahb1_rst 24>;
clocks = <&ccu CLK_AHB1_OTG>;
resets = <&ccu RST_AHB1_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
@@ -565,15 +343,15 @@
reg-names = "phy_ctrl",
"pmu1",
"pmu2";
clocks = <&usb_clk 8>,
<&usb_clk 9>,
<&usb_clk 10>;
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>,
<&ccu CLK_USB_PHY2>;
clock-names = "usb0_phy",
"usb1_phy",
"usb2_phy";
resets = <&usb_clk 0>,
<&usb_clk 1>,
<&usb_clk 2>;
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>,
<&ccu RST_USB_PHY2>;
reset-names = "usb0_reset",
"usb1_reset",
"usb2_reset";
@@ -585,8 +363,8 @@
compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 26>;
resets = <&ahb1_rst 26>;
clocks = <&ccu CLK_AHB1_EHCI0>;
resets = <&ccu RST_AHB1_EHCI0>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
@@ -596,8 +374,8 @@
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 29>, <&usb_clk 16>;
resets = <&ahb1_rst 29>;
clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_AHB1_OHCI0>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
@@ -607,8 +385,8 @@
compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 27>;
resets = <&ahb1_rst 27>;
clocks = <&ccu CLK_AHB1_EHCI1>;
resets = <&ccu RST_AHB1_EHCI1>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
@@ -618,8 +396,8 @@
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
reg = <0x01c1b400 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 30>, <&usb_clk 17>;
resets = <&ahb1_rst 30>;
clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_AHB1_OHCI1>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
@@ -629,11 +407,20 @@
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
reg = <0x01c1c400 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 31>, <&usb_clk 18>;
resets = <&ahb1_rst 31>;
clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
resets = <&ccu RST_AHB1_OHCI2>;
status = "disabled";
};
ccu: clock@01c20000 {
compatible = "allwinner,sun6i-a31-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
pio: pinctrl@01c20800 {
compatible = "allwinner,sun6i-a31-pinctrl";
reg = <0x01c20800 0x400>;
@@ -641,7 +428,7 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 5>;
clocks = <&ccu CLK_APB1_PIO>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -762,24 +549,6 @@
};
};
ahb1_rst: reset@01c202c0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-ahb1-reset";
reg = <0x01c202c0 0xc>;
};
apb1_rst: reset@01c202d0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d0 0x4>;
};
apb2_rst: reset@01c202d8 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d8 0x4>;
};
timer@01c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
@@ -816,8 +585,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 16>;
resets = <&apb2_rst 16>;
clocks = <&ccu CLK_APB2_UART0>;
resets = <&ccu RST_APB2_UART0>;
dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx";
status = "disabled";
@@ -829,8 +598,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 17>;
resets = <&apb2_rst 17>;
clocks = <&ccu CLK_APB2_UART1>;
resets = <&ccu RST_APB2_UART1>;
dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx";
status = "disabled";
@@ -842,8 +611,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 18>;
resets = <&apb2_rst 18>;
clocks = <&ccu CLK_APB2_UART2>;
resets = <&ccu RST_APB2_UART2>;
dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx";
status = "disabled";
@@ -855,8 +624,8 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 19>;
resets = <&apb2_rst 19>;
clocks = <&ccu CLK_APB2_UART3>;
resets = <&ccu RST_APB2_UART3>;
dmas = <&dma 9>, <&dma 9>;
dma-names = "rx", "tx";
status = "disabled";
@@ -868,8 +637,8 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 20>;
resets = <&apb2_rst 20>;
clocks = <&ccu CLK_APB2_UART4>;
resets = <&ccu RST_APB2_UART4>;
dmas = <&dma 10>, <&dma 10>;
dma-names = "rx", "tx";
status = "disabled";
@@ -881,8 +650,8 @@
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 21>;
resets = <&apb2_rst 21>;
clocks = <&ccu CLK_APB2_UART5>;
resets = <&ccu RST_APB2_UART5>;
dmas = <&dma 22>, <&dma 22>;
dma-names = "rx", "tx";
status = "disabled";
@@ -892,8 +661,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 0>;
resets = <&apb2_rst 0>;
clocks = <&ccu CLK_APB2_I2C0>;
resets = <&ccu RST_APB2_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -903,8 +672,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 1>;
resets = <&apb2_rst 1>;
clocks = <&ccu CLK_APB2_I2C1>;
resets = <&ccu RST_APB2_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -914,8 +683,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 2>;
resets = <&apb2_rst 2>;
clocks = <&ccu CLK_APB2_I2C2>;
resets = <&ccu RST_APB2_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -925,8 +694,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b800 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 3>;
resets = <&apb2_rst 3>;
clocks = <&ccu CLK_APB2_I2C3>;
resets = <&ccu RST_APB2_I2C3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -937,9 +706,9 @@
reg = <0x01c30000 0x1054>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
clock-names = "stmmaceth", "allwinner_gmac_tx";
resets = <&ahb1_rst 17>;
resets = <&ccu RST_AHB1_EMAC>;
reset-names = "stmmaceth";
snps,pbl = <2>;
snps,fixed-burst;
@@ -953,9 +722,9 @@
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 5>, <&ss_clk>;
clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
clock-names = "ahb", "mod";
resets = <&ahb1_rst 5>;
resets = <&ccu RST_AHB1_SS>;
reset-names = "ahb";
};
@@ -967,19 +736,19 @@
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 19>;
resets = <&ahb1_rst 19>;
clocks = <&ccu CLK_AHB1_HSTIMER>;
resets = <&ccu RST_AHB1_HSTIMER>;
};
spi0: spi@01c68000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c68000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 20>, <&spi0_clk>;
clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
resets = <&ahb1_rst 20>;
resets = <&ccu RST_AHB1_SPI0>;
status = "disabled";
};
@@ -987,11 +756,11 @@
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c69000 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 21>, <&spi1_clk>;
clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
dmas = <&dma 24>, <&dma 24>;
dma-names = "rx", "tx";
resets = <&ahb1_rst 21>;
resets = <&ccu RST_AHB1_SPI1>;
status = "disabled";
};
@@ -999,11 +768,11 @@
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c6a000 0x1000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 22>, <&spi2_clk>;
clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
clock-names = "ahb", "mod";
dmas = <&dma 25>, <&dma 25>;
dma-names = "rx", "tx";
resets = <&ahb1_rst 22>;
resets = <&ccu RST_AHB1_SPI2>;
status = "disabled";
};
@@ -1011,11 +780,11 @@
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c6b000 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 23>, <&spi3_clk>;
clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
clock-names = "ahb", "mod";
dmas = <&dma 26>, <&dma 26>;
dma-names = "rx", "tx";
resets = <&ahb1_rst 23>;
resets = <&ccu RST_AHB1_SPI3>;
status = "disabled";
};
@@ -1052,8 +821,9 @@
ar100: ar100_clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
<&pll6 0>;
clocks = <&osc32k>, <&osc24M>,
<&ccu CLK_PLL_PERIPH>,
<&ccu CLK_PLL_PERIPH>;
clock-output-names = "ar100";
};

305
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View File

@@ -46,7 +46,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -60,7 +62,9 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <&pll6 0>;
clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
<&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
status = "disabled";
};
};
@@ -111,151 +115,6 @@
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
/* dummy clock until actually implemented */
pll5: pll5_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
clock-output-names = "pll5";
};
pll6: clk@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6", "pll6x2";
};
cpu: cpu_clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20050 0x4>;
/*
* PLL1 is listed twice here.
* While it looks suspicious, it's actually documented
* that way both in the datasheet and in the code from
* Allwinner.
*/
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
clock-output-names = "cpu";
};
axi: axi_clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-axi-clk";
reg = <0x01c20050 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
};
ahb1: ahb1_clk@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1";
};
apb1: apb1_clk@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1>;
clock-output-names = "apb1";
};
apb1_gates: clk@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
clock-indices = <0>, <5>,
<12>, <13>;
clock-output-names = "apb1_codec", "apb1_pio",
"apb1_daudio0", "apb1_daudio1";
};
apb2: clk@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
clock-output-names = "apb2";
};
apb2_gates: clk@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
clock-indices = <0>, <1>,
<2>, <16>,
<17>, <18>,
<19>, <20>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_uart0",
"apb2_uart1", "apb2_uart2",
"apb2_uart3", "apb2_uart4";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
nand_clk: clk@01c20080 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>;
clock-output-names = "nand";
};
usb_clk: clk@01c200cc {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun8i-a23-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
"usb_hsic_12M", "usb_ohci0";
};
};
soc@01c00000 {
@@ -268,23 +127,23 @@
compatible = "allwinner,sun8i-a23-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 6>;
resets = <&ahb1_rst 6>;
clocks = <&ccu CLK_BUS_DMA>;
resets = <&ccu RST_BUS_DMA>;
#dma-cells = <1>;
};
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb1_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clocks = <&ccu CLK_BUS_MMC0>,
<&ccu CLK_MMC0>,
<&ccu CLK_MMC0_OUTPUT>,
<&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 8>;
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -295,15 +154,15 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ahb1_gates 9>,
<&mmc1_clk 0>,
<&mmc1_clk 1>,
<&mmc1_clk 2>;
clocks = <&ccu CLK_BUS_MMC1>,
<&ccu CLK_MMC1>,
<&ccu CLK_MMC1_OUTPUT>,
<&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 9>;
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -314,15 +173,15 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb1_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clocks = <&ccu CLK_BUS_MMC2>,
<&ccu CLK_MMC2>,
<&ccu CLK_MMC2_OUTPUT>,
<&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 10>;
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -334,21 +193,51 @@
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 13>, <&nand_clk>;
clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
clock-names = "ahb", "mod";
resets = <&ahb1_rst 13>;
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@01c19000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c19000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@01c19400 {
/*
* compatible and address regions get set in
* SoC specific dtsi file
*/
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci0: usb@01c1a000 {
compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 26>;
resets = <&ahb1_rst 26>;
clocks = <&ccu CLK_BUS_EHCI>;
resets = <&ccu RST_BUS_EHCI>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
@@ -358,18 +247,26 @@
compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 29>, <&usb_clk 16>;
resets = <&ahb1_rst 29>;
clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
resets = <&ccu RST_BUS_OHCI>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ccu: clock@01c20000 {
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
};
pio: pinctrl@01c20800 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c20800 0x400>;
/* interrupts get set in SoC specific dtsi file */
clocks = <&apb1_gates 5>;
clocks = <&ccu CLK_BUS_PIO>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
@@ -382,6 +279,16 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_pins_a: uart1@0 {
allwinner,pins = "PG6", "PG7";
allwinner,function = "uart1";
};
uart1_pins_cts_rts_a: uart1-cts-rts@0 {
allwinner,pins = "PG8", "PG9";
allwinner,function = "uart1";
};
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
@@ -435,24 +342,16 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
ahb1_rst: reset@01c202c0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202c0 0xc>;
};
apb1_rst: reset@01c202d0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d0 0x4>;
};
apb2_rst: reset@01c202d8 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d8 0x4>;
lcd_rgb666_pins: lcd-rgb666@0 {
allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
"PD24", "PD25", "PD26", "PD27";
allwinner,function = "lcd0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
timer@01c20c00 {
@@ -490,8 +389,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 16>;
resets = <&apb2_rst 16>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx";
status = "disabled";
@@ -503,8 +402,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 17>;
resets = <&apb2_rst 17>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx";
status = "disabled";
@@ -516,8 +415,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 18>;
resets = <&apb2_rst 18>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx";
status = "disabled";
@@ -529,8 +428,8 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 19>;
resets = <&apb2_rst 19>;
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
dmas = <&dma 9>, <&dma 9>;
dma-names = "rx", "tx";
status = "disabled";
@@ -542,8 +441,8 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 20>;
resets = <&apb2_rst 20>;
clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>;
dmas = <&dma 10>, <&dma 10>;
dma-names = "rx", "tx";
status = "disabled";
@@ -553,8 +452,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 0>;
resets = <&apb2_rst 0>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -564,8 +463,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 1>;
resets = <&apb2_rst 1>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -575,8 +474,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb2_gates 2>;
resets = <&apb2_rst 2>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

9
arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts
View File

@@ -53,6 +53,15 @@
status = "okay";
};
&touchscreen {
reg = <0x40>;
compatible = "silead,gsl3675";
firmware-name = "gsl3675-gt90h.fw";
touchscreen-size-x = <1792>;
touchscreen-size-y = <1024>;
status = "okay";
};
&lradc {
button@600 {
label = "Back";

9
arch/arm/boot/dts/sun8i-a23-inet86dz.dts
View File

@@ -53,6 +53,15 @@
status = "okay";
};
&touchscreen {
reg = <0x40>;
compatible = "silead,gsl1680";
firmware-name = "gsl1680-inet86dz.fw";
touchscreen-size-x = <960>;
touchscreen-size-y = <640>;
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_dldo1>;
};

26
arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
View File

@@ -62,6 +62,13 @@
};
};
&i2c1 {
mma7660: accelerometer@4c {
reg = <0x4c>;
compatible = "fsl,mma7660";
};
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
@@ -90,3 +97,22 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
&reg_ldo_io1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-touchscreen";
status = "okay";
};
&touchscreen {
reg = <0x40>;
compatible = "silead,gsl1680";
firmware-name = "gsl1680-polaroid-mid2407pxe03.fw";
touchscreen-size-x = <960>;
touchscreen-size-y = <640>;
touchscreen-inverted-x;
touchscreen-inverted-y;
vddio-supply = <&reg_ldo_io1>;
status = "okay";
};

9
arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts
View File

@@ -90,3 +90,12 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
&touchscreen {
reg = <0x40>;
compatible = "silead,gsl3670";
firmware-name = "gsl3670-polaroid-mid2809pxe04.fw";
touchscreen-size-x = <1660>;
touchscreen-size-y = <890>;
status = "okay";
};

80
arch/arm/boot/dts/sun8i-a23.dtsi
View File

@@ -48,74 +48,10 @@
memory {
reg = <0x40000000 0x40000000>;
};
};
clocks {
ahb1_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
clock-indices = <1>, <6>,
<8>, <9>, <10>,
<13>, <14>,
<19>, <20>,
<21>, <24>, <26>,
<29>, <32>, <36>,
<40>, <44>, <46>,
<52>, <53>,
<54>, <57>;
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
"ahb1_nand", "ahb1_sdram",
"ahb1_hstimer", "ahb1_spi0",
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
"ahb1_csi", "ahb1_be", "ahb1_fe",
"ahb1_gpu", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_drc";
};
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
};
soc@01c00000 {
usb_otg: usb@01c19000 {
compatible = "allwinner,sun6i-a31-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ahb1_gates 24>;
resets = <&ahb1_rst 24>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@01c19400 {
compatible = "allwinner,sun8i-a23-usb-phy";
reg = <0x01c19400 0x10>,
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu1";
clocks = <&usb_clk 8>,
<&usb_clk 9>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&usb_clk 0>,
<&usb_clk 1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
};
&ccu {
compatible = "allwinner,sun8i-a23-ccu";
};
&pio {
@@ -124,3 +60,13 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
};
&usb_otg {
compatible = "allwinner,sun6i-a31-musb";
};
&usbphy {
compatible = "allwinner,sun8i-a23-usb-phy";
reg = <0x01c19400 0x10>, <0x01c1a800 0x4>;
reg-names = "phy_ctrl", "pmu1";
};

10
arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
View File

@@ -58,6 +58,16 @@
status = "okay";
};
&touchscreen {
reg = <0x40>;
compatible = "silead,gsl3675";
firmware-name = "gsl3675-ga10h.fw";
touchscreen-size-x = <1630>;
touchscreen-size-y = <990>;
touchscreen-inverted-y;
status = "okay";
};
&lradc {
button@600 {
label = "Back";

20
arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
View File

@@ -49,6 +49,15 @@
model = "INet-D978 Rev 02";
compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33";
aliases {
serial0 = &uart1;
};
chosen {
/* Delete debug UART as serial0 is the UART for bluetooth */
/delete-property/stdout-path;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -86,3 +95,14 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
&r_uart {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>,
<&uart1_pins_cts_rts_a>;
status = "okay";
};

244
arch/arm/boot/dts/sun8i-a33.dtsi
View File

@@ -59,107 +59,179 @@
};
};
de: display-engine {
compatible = "allwinner,sun8i-a33-display-engine";
allwinner,pipelines = <&fe0>;
status = "disabled";
};
memory {
reg = <0x40000000 0x80000000>;
};
clocks {
/* Dummy clock for pll11 (DDR1) until actually implemented */
pll11: pll11_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
clock-output-names = "pll11";
};
ahb1_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a33-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
clock-indices = <1>, <5>,
<6>, <8>, <9>,
<10>, <13>, <14>,
<19>, <20>,
<21>, <24>, <26>,
<29>, <32>, <36>,
<40>, <44>, <46>,
<52>, <53>,
<54>, <57>,
<58>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma","ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_nand", "ahb1_sdram",
"ahb1_hstimer", "ahb1_spi0",
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
"ahb1_csi", "ahb1_be", "ahb1_fe",
"ahb1_gpu", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_drc",
"ahb1_sat";
};
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "ss";
};
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>;
clock-output-names = "mbus";
};
};
soc@01c00000 {
tcon0: lcd-controller@01c0c000 {
compatible = "allwinner,sun8i-a33-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LCD>,
<&ccu CLK_LCD_CH0>;
clock-names = "ahb",
"tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_LCD>;
reset-names = "lcd";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon0_in_drc0: endpoint@0 {
reg = <0>;
remote-endpoint = <&drc0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
crypto: crypto-engine@01c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb1_gates 5>, <&ss_clk>;
clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
clock-names = "ahb", "mod";
resets = <&ahb1_rst 5>;
resets = <&ccu RST_BUS_SS>;
reset-names = "ahb";
};
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
clocks = <&ahb1_gates 24>;
resets = <&ahb1_rst 24>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
fe0: display-frontend@01e00000 {
compatible = "allwinner,sun8i-a33-display-frontend";
reg = <0x01e00000 0x20000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
<&ccu CLK_DRAM_DE_FE>;
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_BUS_DE_FE>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
fe0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
fe0_out_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_in_fe0>;
};
};
};
};
usbphy: phy@01c19400 {
compatible = "allwinner,sun8i-a33-usb-phy";
reg = <0x01c19400 0x14>,
<0x01c1a800 0x4>;
reg-names = "phy_ctrl",
"pmu1";
clocks = <&usb_clk 8>,
<&usb_clk 9>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&usb_clk 0>,
<&usb_clk 1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
be0: display-backend@01e60000 {
compatible = "allwinner,sun8i-a33-display-backend";
reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
reg-names = "be", "sat";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
clock-names = "ahb", "mod",
"ram", "sat";
resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
reset-names = "be", "sat";
assigned-clocks = <&ccu CLK_DE_BE>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
be0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
be0_in_fe0: endpoint@0 {
reg = <0>;
remote-endpoint = <&fe0_out_be0>;
};
};
be0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
be0_out_drc0: endpoint@0 {
reg = <0>;
remote-endpoint = <&drc0_in_be0>;
};
};
};
};
drc0: drc@01e70000 {
compatible = "allwinner,sun8i-a33-drc";
reg = <0x01e70000 0x10000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
<&ccu CLK_DRAM_DRC>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_BUS_DRC>;
assigned-clocks = <&ccu CLK_DRC>;
assigned-clock-rates = <300000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
drc0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
drc0_in_be0: endpoint@0 {
reg = <0>;
remote-endpoint = <&be0_out_drc0>;
};
};
drc0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
drc0_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon0_in_drc0>;
};
};
};
};
};
};
&ccu {
compatible = "allwinner,sun8i-a33-ccu";
};
&pio {
compatible = "allwinner,sun8i-a33-pinctrl";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
@@ -173,3 +245,13 @@
};
};
&usb_otg {
compatible = "allwinner,sun8i-a33-musb";
};
&usbphy {
compatible = "allwinner,sun8i-a33-usb-phy";
reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
reg-names = "phy_ctrl", "pmu1";
};

2
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
View File

@@ -185,7 +185,7 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};

18
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
View File

@@ -186,6 +186,24 @@
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "disabled";
};
&usb1_vbus_pin_a {
allwinner,pins = "PG13";
};

18
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
View File

@@ -139,6 +139,24 @@
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "disabled";
};
&usbphy {
/* USB VBUS is always on */
status = "okay";

18
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
View File

@@ -161,6 +161,24 @@
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "disabled";
};
&usbphy {
/* USB VBUS is always on */
status = "okay";

85
arch/arm/boot/dts/sun8i-h3.dtsi
View File

@@ -327,6 +327,27 @@
interrupt-controller;
#interrupt-cells = <3>;
i2c0_pins: i2c0 {
allwinner,pins = "PA11", "PA12";
allwinner,function = "i2c0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins: i2c1 {
allwinner,pins = "PA18", "PA19";
allwinner,function = "i2c1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins: i2c2 {
allwinner,pins = "PE12", "PE13";
allwinner,function = "i2c2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
@@ -367,12 +388,33 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_pins_a: uart1@0 {
allwinner,pins = "PG6", "PG7", "PG8", "PG9";
uart1_pins: uart1 {
allwinner,pins = "PG6", "PG7";
allwinner,function = "uart1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart1_rts_cts_pins: uart1_rts_cts {
allwinner,pins = "PG8", "PG9";
allwinner,function = "uart1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart2_pins: uart2 {
allwinner,pins = "PA0", "PA1";
allwinner,function = "uart2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart3_pins: uart3 {
allwinner,pins = "PG13", "PG14";
allwinner,function = "uart3";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
timer@01c20c00 {
@@ -449,6 +491,45 @@
status = "disabled";
};
i2c0: i2c@01c2ac00 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@01c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@01c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,

116
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
View File

@@ -253,6 +253,122 @@
reg_rtc_ldo: rtc_ldo {
regulator-name = "vcc-rtc-vdd1v8-io";
};
sw {
/* unused */
};
};
};
axp806: pmic@745 {
compatible = "x-powers,axp806";
reg = <0x745>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
bldoin-supply = <&reg_dcdce>;
regulators {
reg_s_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
aldo2 {
/*
* unused, but use a different name to
* avoid name clash with axp809's aldo's
*/
regulator-name = "s_aldo2";
};
aldo3 {
/*
* unused, but use a different name to
* avoid name clash with axp809's aldo's
*/
regulator-name = "s_aldo3";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-name = "vcc18-efuse-adc-display-csi";
};
reg_bldo2: bldo2 {
regulator-always-on;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-name =
"vdd18-drampll-vcc18-pll-cpvdd";
};
bldo3 {
/* unused */
};
reg_bldo4: bldo4 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vcc12-hsic";
};
reg_cldo1: cldo1 {
/*
* This was 3V in the original design, but
* 3.3V is the recommended supply voltage
* for the Ethernet PHY.
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-gmac-phy";
};
reg_cldo2: cldo2 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "afvcc-cam";
};
reg_cldo3: cldo3 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-io-wifi-codec-io2";
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpub";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-vpu";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <2100000>;
regulator-max-microvolt = <2100000>;
regulator-name = "vcc-bldo-codec-ldoin";
};
sw {
/*
* unused, but use a different name to
* avoid name clash with axp809's sw
*/
regulator-name = "s_sw";
};
};
};

123
arch/arm/boot/dts/sun9i-a80-optimus.dts
View File

@@ -112,7 +112,8 @@
};
&ehci1 {
status = "okay";
/* Enable if HSIC peripheral is connected */
status = "disabled";
};
&ehci2 {
@@ -325,6 +326,122 @@
reg_rtc_ldo: rtc_ldo {
regulator-name = "vcc-rtc-vdd1v8-io";
};
sw {
/* unused */
};
};
};
axp806: pmic@745 {
compatible = "x-powers,axp806";
reg = <0x745>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
bldoin-supply = <&reg_dcdce>;
regulators {
reg_s_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
aldo2 {
/*
* unused, but use a different name to
* avoid name clash with axp809's aldo's
*/
regulator-name = "s_aldo2";
};
aldo3 {
/*
* unused, but use a different name to
* avoid name clash with axp809's aldo's
*/
regulator-name = "s_aldo3";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-name = "vcc18-efuse-adc-display-csi";
};
reg_bldo2: bldo2 {
regulator-always-on;
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-name =
"vdd18-drampll-vcc18-pll-cpvdd";
};
bldo3 {
/* unused */
};
reg_bldo4: bldo4 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vcc12-hsic";
};
reg_cldo1: cldo1 {
/*
* This was 3V in the original design, but
* 3.3V is the recommended supply voltage
* for the Ethernet PHY.
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-gmac-phy";
};
reg_cldo2: cldo2 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "afvcc-cam";
};
reg_cldo3: cldo3 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-io-wifi-codec-io2";
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpub";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-vpu";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <2100000>;
regulator-max-microvolt = <2100000>;
regulator-name = "vcc-bldo-codec-ldoin";
};
sw {
/*
* unused, but use a different name to
* avoid name clash with axp809's sw
*/
regulator-name = "s_sw";
};
};
};
@@ -367,7 +484,9 @@
};
&usbphy2 {
status = "okay";
phy-supply = <&reg_bldo4>;
/* Enable if HSIC peripheral is connected */
status = "disabled";
};
&usbphy3 {