Merge tag 'ntb-4.15' of git://github.com/jonmason/ntb
Pull ntb updates from Jon Mason: "Support for the switchtec ntb and related changes. Also, a couple of bug fixes" [ The timing isn't great. I had asked people to send me pull requests before my family vacation, and this code has not even been in linux-next as far as I can tell. But Logan Gunthorpe pleaded for its inclusion because the Switchtec driver has apparently been around for a while, just never in linux-next - Linus ] * tag 'ntb-4.15' of git://github.com/jonmason/ntb: ntb: intel: remove b2b memory window workaround for Skylake NTB NTB: make idt_89hpes_cfg const NTB: switchtec_ntb: Update switchtec documentation with notes for NTB NTB: switchtec_ntb: Add memory window support NTB: switchtec_ntb: Implement scratchpad registers NTB: switchtec_ntb: Implement doorbell registers NTB: switchtec_ntb: Add link management NTB: switchtec_ntb: Add skeleton NTB driver NTB: switchtec_ntb: Initialize hardware for doorbells and messages NTB: switchtec_ntb: Initialize hardware for memory windows NTB: switchtec_ntb: Introduce initial NTB driver NTB: Add check and comment for link up to mw_count() and mw_get_align() NTB: Ensure ntb_mw_get_align() is only called when the link is up NTB: switchtec: Add link event notifier callback NTB: switchtec: Add NTB hardware register definitions NTB: switchtec: Export class symbol for use in upper layer driver NTB: switchtec: Move structure definitions into a common header ntb: update maintainer list for Intel NTB driver
このコミットが含まれているのは:
Linus Torvalds
@@ -13,6 +13,7 @@
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*
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*/
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#include <linux/switchtec.h>
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#include <linux/switchtec_ioctl.h>
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#include <linux/interrupt.h>
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@@ -20,8 +21,6 @@
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#include <linux/fs.h>
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#include <linux/uaccess.h>
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#include <linux/poll.h>
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#include <linux/pci.h>
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#include <linux/cdev.h>
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#include <linux/wait.h>
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MODULE_DESCRIPTION("Microsemi Switchtec(tm) PCIe Management Driver");
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@@ -34,265 +33,10 @@ module_param(max_devices, int, 0644);
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MODULE_PARM_DESC(max_devices, "max number of switchtec device instances");
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static dev_t switchtec_devt;
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static struct class *switchtec_class;
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static DEFINE_IDA(switchtec_minor_ida);
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#define MICROSEMI_VENDOR_ID 0x11f8
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#define MICROSEMI_NTB_CLASSCODE 0x068000
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#define MICROSEMI_MGMT_CLASSCODE 0x058000
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#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
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#define SWITCHTEC_MAX_PFF_CSR 48
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#define SWITCHTEC_EVENT_OCCURRED BIT(0)
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#define SWITCHTEC_EVENT_CLEAR BIT(0)
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#define SWITCHTEC_EVENT_EN_LOG BIT(1)
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#define SWITCHTEC_EVENT_EN_CLI BIT(2)
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#define SWITCHTEC_EVENT_EN_IRQ BIT(3)
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#define SWITCHTEC_EVENT_FATAL BIT(4)
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enum {
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SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
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SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
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SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
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SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
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SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
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SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
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SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
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SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
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};
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struct mrpc_regs {
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u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
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u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
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u32 cmd;
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u32 status;
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u32 ret_value;
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} __packed;
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enum mrpc_status {
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SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
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SWITCHTEC_MRPC_STATUS_DONE = 2,
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SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
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SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
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};
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struct sw_event_regs {
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u64 event_report_ctrl;
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u64 reserved1;
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u64 part_event_bitmap;
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u64 reserved2;
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u32 global_summary;
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u32 reserved3[3];
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u32 stack_error_event_hdr;
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u32 stack_error_event_data;
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u32 reserved4[4];
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u32 ppu_error_event_hdr;
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u32 ppu_error_event_data;
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u32 reserved5[4];
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u32 isp_error_event_hdr;
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u32 isp_error_event_data;
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u32 reserved6[4];
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u32 sys_reset_event_hdr;
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u32 reserved7[5];
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u32 fw_exception_hdr;
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u32 reserved8[5];
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u32 fw_nmi_hdr;
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u32 reserved9[5];
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u32 fw_non_fatal_hdr;
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u32 reserved10[5];
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u32 fw_fatal_hdr;
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u32 reserved11[5];
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u32 twi_mrpc_comp_hdr;
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u32 twi_mrpc_comp_data;
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u32 reserved12[4];
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u32 twi_mrpc_comp_async_hdr;
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u32 twi_mrpc_comp_async_data;
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u32 reserved13[4];
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u32 cli_mrpc_comp_hdr;
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u32 cli_mrpc_comp_data;
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u32 reserved14[4];
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u32 cli_mrpc_comp_async_hdr;
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u32 cli_mrpc_comp_async_data;
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u32 reserved15[4];
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u32 gpio_interrupt_hdr;
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u32 gpio_interrupt_data;
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u32 reserved16[4];
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} __packed;
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enum {
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SWITCHTEC_CFG0_RUNNING = 0x04,
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SWITCHTEC_CFG1_RUNNING = 0x05,
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SWITCHTEC_IMG0_RUNNING = 0x03,
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SWITCHTEC_IMG1_RUNNING = 0x07,
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};
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struct sys_info_regs {
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u32 device_id;
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u32 device_version;
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u32 firmware_version;
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u32 reserved1;
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u32 vendor_table_revision;
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u32 table_format_version;
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u32 partition_id;
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u32 cfg_file_fmt_version;
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u16 cfg_running;
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u16 img_running;
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u32 reserved2[57];
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char vendor_id[8];
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char product_id[16];
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char product_revision[4];
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char component_vendor[8];
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u16 component_id;
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u8 component_revision;
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} __packed;
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struct flash_info_regs {
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u32 flash_part_map_upd_idx;
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struct active_partition_info {
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u32 address;
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u32 build_version;
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u32 build_string;
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} active_img;
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struct active_partition_info active_cfg;
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struct active_partition_info inactive_img;
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struct active_partition_info inactive_cfg;
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u32 flash_length;
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struct partition_info {
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u32 address;
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u32 length;
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} cfg0;
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struct partition_info cfg1;
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struct partition_info img0;
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struct partition_info img1;
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struct partition_info nvlog;
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struct partition_info vendor[8];
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};
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struct ntb_info_regs {
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u8 partition_count;
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u8 partition_id;
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u16 reserved1;
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u64 ep_map;
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u16 requester_id;
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} __packed;
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struct part_cfg_regs {
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u32 status;
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u32 state;
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u32 port_cnt;
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u32 usp_port_mode;
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u32 usp_pff_inst_id;
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u32 vep_pff_inst_id;
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u32 dsp_pff_inst_id[47];
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u32 reserved1[11];
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u16 vep_vector_number;
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u16 usp_vector_number;
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u32 port_event_bitmap;
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u32 reserved2[3];
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u32 part_event_summary;
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u32 reserved3[3];
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u32 part_reset_hdr;
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u32 part_reset_data[5];
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u32 mrpc_comp_hdr;
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u32 mrpc_comp_data[5];
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u32 mrpc_comp_async_hdr;
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u32 mrpc_comp_async_data[5];
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u32 dyn_binding_hdr;
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u32 dyn_binding_data[5];
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u32 reserved4[159];
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} __packed;
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enum {
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SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
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SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
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SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
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SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
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};
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struct pff_csr_regs {
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u16 vendor_id;
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u16 device_id;
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u32 pci_cfg_header[15];
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u32 pci_cap_region[48];
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u32 pcie_cap_region[448];
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u32 indirect_gas_window[128];
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u32 indirect_gas_window_off;
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u32 reserved[127];
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u32 pff_event_summary;
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u32 reserved2[3];
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u32 aer_in_p2p_hdr;
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u32 aer_in_p2p_data[5];
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u32 aer_in_vep_hdr;
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u32 aer_in_vep_data[5];
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u32 dpc_hdr;
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u32 dpc_data[5];
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u32 cts_hdr;
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u32 cts_data[5];
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u32 reserved3[6];
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u32 hotplug_hdr;
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u32 hotplug_data[5];
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u32 ier_hdr;
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u32 ier_data[5];
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u32 threshold_hdr;
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u32 threshold_data[5];
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u32 power_mgmt_hdr;
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u32 power_mgmt_data[5];
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u32 tlp_throttling_hdr;
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u32 tlp_throttling_data[5];
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u32 force_speed_hdr;
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u32 force_speed_data[5];
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u32 credit_timeout_hdr;
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u32 credit_timeout_data[5];
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u32 link_state_hdr;
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u32 link_state_data[5];
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u32 reserved4[174];
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} __packed;
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struct switchtec_dev {
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struct pci_dev *pdev;
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struct device dev;
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struct cdev cdev;
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int partition;
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int partition_count;
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int pff_csr_count;
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char pff_local[SWITCHTEC_MAX_PFF_CSR];
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void __iomem *mmio;
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struct mrpc_regs __iomem *mmio_mrpc;
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struct sw_event_regs __iomem *mmio_sw_event;
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struct sys_info_regs __iomem *mmio_sys_info;
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struct flash_info_regs __iomem *mmio_flash_info;
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struct ntb_info_regs __iomem *mmio_ntb;
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struct part_cfg_regs __iomem *mmio_part_cfg;
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struct part_cfg_regs __iomem *mmio_part_cfg_all;
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struct pff_csr_regs __iomem *mmio_pff_csr;
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/*
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* The mrpc mutex must be held when accessing the other
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* mrpc_ fields, alive flag and stuser->state field
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*/
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struct mutex mrpc_mutex;
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struct list_head mrpc_queue;
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int mrpc_busy;
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struct work_struct mrpc_work;
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struct delayed_work mrpc_timeout;
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bool alive;
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wait_queue_head_t event_wq;
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atomic_t event_cnt;
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};
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static struct switchtec_dev *to_stdev(struct device *dev)
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{
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return container_of(dev, struct switchtec_dev, dev);
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}
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struct class *switchtec_class;
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EXPORT_SYMBOL_GPL(switchtec_class);
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enum mrpc_state {
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MRPC_IDLE = 0,
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@@ -1234,6 +978,49 @@ static const struct file_operations switchtec_fops = {
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.compat_ioctl = switchtec_dev_ioctl,
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};
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static void link_event_work(struct work_struct *work)
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{
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struct switchtec_dev *stdev;
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stdev = container_of(work, struct switchtec_dev, link_event_work);
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if (stdev->link_notifier)
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stdev->link_notifier(stdev);
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}
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static void check_link_state_events(struct switchtec_dev *stdev)
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{
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int idx;
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u32 reg;
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int count;
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int occurred = 0;
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for (idx = 0; idx < stdev->pff_csr_count; idx++) {
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reg = ioread32(&stdev->mmio_pff_csr[idx].link_state_hdr);
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dev_dbg(&stdev->dev, "link_state: %d->%08x\n", idx, reg);
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count = (reg >> 5) & 0xFF;
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if (count != stdev->link_event_count[idx]) {
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occurred = 1;
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stdev->link_event_count[idx] = count;
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}
|
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}
|
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if (occurred)
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schedule_work(&stdev->link_event_work);
|
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}
|
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|
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static void enable_link_state_events(struct switchtec_dev *stdev)
|
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{
|
||||
int idx;
|
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|
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for (idx = 0; idx < stdev->pff_csr_count; idx++) {
|
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iowrite32(SWITCHTEC_EVENT_CLEAR |
|
||||
SWITCHTEC_EVENT_EN_IRQ,
|
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&stdev->mmio_pff_csr[idx].link_state_hdr);
|
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}
|
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}
|
||||
|
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static void stdev_release(struct device *dev)
|
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{
|
||||
struct switchtec_dev *stdev = to_stdev(dev);
|
||||
@@ -1286,6 +1073,7 @@ static struct switchtec_dev *stdev_create(struct pci_dev *pdev)
|
||||
stdev->mrpc_busy = 0;
|
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INIT_WORK(&stdev->mrpc_work, mrpc_event_work);
|
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INIT_DELAYED_WORK(&stdev->mrpc_timeout, mrpc_timeout_work);
|
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INIT_WORK(&stdev->link_event_work, link_event_work);
|
||||
init_waitqueue_head(&stdev->event_wq);
|
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atomic_set(&stdev->event_cnt, 0);
|
||||
|
||||
@@ -1329,6 +1117,9 @@ static int mask_event(struct switchtec_dev *stdev, int eid, int idx)
|
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if (!(hdr & SWITCHTEC_EVENT_OCCURRED && hdr & SWITCHTEC_EVENT_EN_IRQ))
|
||||
return 0;
|
||||
|
||||
if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE)
|
||||
return 0;
|
||||
|
||||
dev_dbg(&stdev->dev, "%s: %d %d %x\n", __func__, eid, idx, hdr);
|
||||
hdr &= ~(SWITCHTEC_EVENT_EN_IRQ | SWITCHTEC_EVENT_OCCURRED);
|
||||
iowrite32(hdr, hdr_reg);
|
||||
@@ -1348,6 +1139,7 @@ static int mask_all_events(struct switchtec_dev *stdev, int eid)
|
||||
for (idx = 0; idx < stdev->pff_csr_count; idx++) {
|
||||
if (!stdev->pff_local[idx])
|
||||
continue;
|
||||
|
||||
count += mask_event(stdev, eid, idx);
|
||||
}
|
||||
} else {
|
||||
@@ -1372,6 +1164,8 @@ static irqreturn_t switchtec_event_isr(int irq, void *dev)
|
||||
iowrite32(reg, &stdev->mmio_part_cfg->mrpc_comp_hdr);
|
||||
}
|
||||
|
||||
check_link_state_events(stdev);
|
||||
|
||||
for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++)
|
||||
event_count += mask_all_events(stdev, eid);
|
||||
|
||||
@@ -1481,6 +1275,9 @@ static int switchtec_pci_probe(struct pci_dev *pdev,
|
||||
struct switchtec_dev *stdev;
|
||||
int rc;
|
||||
|
||||
if (pdev->class == MICROSEMI_NTB_CLASSCODE)
|
||||
request_module_nowait("ntb_hw_switchtec");
|
||||
|
||||
stdev = stdev_create(pdev);
|
||||
if (IS_ERR(stdev))
|
||||
return PTR_ERR(stdev);
|
||||
@@ -1498,6 +1295,7 @@ static int switchtec_pci_probe(struct pci_dev *pdev,
|
||||
iowrite32(SWITCHTEC_EVENT_CLEAR |
|
||||
SWITCHTEC_EVENT_EN_IRQ,
|
||||
&stdev->mmio_part_cfg->mrpc_comp_hdr);
|
||||
enable_link_state_events(stdev);
|
||||
|
||||
rc = cdev_device_add(&stdev->cdev, &stdev->dev);
|
||||
if (rc)
|
||||
|
||||
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