Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull locking updates from Ingo Molnar:
"The locking tree was busier in this cycle than the usual pattern - a
couple of major projects happened to coincide.
The main changes are:
- implement the atomic_fetch_{add,sub,and,or,xor}() API natively
across all SMP architectures (Peter Zijlstra)
- add atomic_fetch_{inc/dec}() as well, using the generic primitives
(Davidlohr Bueso)
- optimize various aspects of rwsems (Jason Low, Davidlohr Bueso,
Waiman Long)
- optimize smp_cond_load_acquire() on arm64 and implement LSE based
atomic{,64}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
on arm64 (Will Deacon)
- introduce smp_acquire__after_ctrl_dep() and fix various barrier
mis-uses and bugs (Peter Zijlstra)
- after discovering ancient spin_unlock_wait() barrier bugs in its
implementation and usage, strengthen its semantics and update/fix
usage sites (Peter Zijlstra)
- optimize mutex_trylock() fastpath (Peter Zijlstra)
- ... misc fixes and cleanups"
* 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (67 commits)
locking/atomic: Introduce inc/dec variants for the atomic_fetch_$op() API
locking/barriers, arch/arm64: Implement LDXR+WFE based smp_cond_load_acquire()
locking/static_keys: Fix non static symbol Sparse warning
locking/qspinlock: Use __this_cpu_dec() instead of full-blown this_cpu_dec()
locking/atomic, arch/tile: Fix tilepro build
locking/atomic, arch/m68k: Remove comment
locking/atomic, arch/arc: Fix build
locking/Documentation: Clarify limited control-dependency scope
locking/atomic, arch/rwsem: Employ atomic_long_fetch_add()
locking/atomic, arch/qrwlock: Employ atomic_fetch_add_acquire()
locking/atomic, arch/mips: Convert to _relaxed atomics
locking/atomic, arch/alpha: Convert to _relaxed atomics
locking/atomic: Remove the deprecated atomic_{set,clear}_mask() functions
locking/atomic: Remove linux/atomic.h:atomic_fetch_or()
locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
locking/atomic: Fix atomic64_relaxed() bits
locking/atomic, arch/xtensa: Implement atomic_fetch_{add,sub,and,or,xor}()
locking/atomic, arch/x86: Implement atomic{,64}_fetch_{add,sub,and,or,xor}()
locking/atomic, arch/tile: Implement atomic{,64}_fetch_{add,sub,and,or,xor}()
locking/atomic, arch/sparc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}()
...
This commit is contained in:
Linus Torvalds
@@ -67,6 +67,33 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
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return val; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned int val, orig; \
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\
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/* \
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* Explicit full memory barrier needed before/after as \
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* LLOCK/SCOND thmeselves don't provide any such semantics \
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*/ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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"1: llock %[orig], [%[ctr]] \n" \
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" " #asm_op " %[val], %[orig], %[i] \n" \
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" scond %[val], [%[ctr]] \n" \
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" \n" \
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: [val] "=&r" (val), \
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[orig] "=&r" (orig) \
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: [ctr] "r" (&v->counter), \
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[i] "ir" (i) \
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: "cc"); \
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\
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smp_mb(); \
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\
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return orig; \
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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#ifndef CONFIG_SMP
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@@ -129,25 +156,44 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
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return temp; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned long flags; \
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unsigned long orig; \
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\
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/* \
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* spin lock/unlock provides the needed smp_mb() before/after \
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*/ \
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atomic_ops_lock(flags); \
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orig = v->counter; \
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v->counter c_op i; \
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atomic_ops_unlock(flags); \
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\
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return orig; \
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}
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#endif /* !CONFIG_ARC_HAS_LLSC */
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op)
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, add)
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ATOMIC_OPS(sub, -=, sub)
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#define atomic_andnot atomic_andnot
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ATOMIC_OP(and, &=, and)
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ATOMIC_OP(andnot, &= ~, bic)
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ATOMIC_OP(or, |=, or)
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ATOMIC_OP(xor, ^=, xor)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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#undef SCOND_FAIL_RETRY_VAR_DEF
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#undef SCOND_FAIL_RETRY_ASM
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#undef SCOND_FAIL_RETRY_VARS
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ATOMIC_OPS(and, &=, and)
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ATOMIC_OPS(andnot, &= ~, bic)
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ATOMIC_OPS(or, |=, or)
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ATOMIC_OPS(xor, ^=, xor)
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#else /* CONFIG_ARC_PLAT_EZNPS */
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@@ -208,22 +254,51 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
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return temp; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static inline int atomic_fetch_##op(int i, atomic_t *v) \
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{ \
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unsigned int temp = i; \
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\
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/* Explicit full memory barrier needed before/after */ \
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smp_mb(); \
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\
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__asm__ __volatile__( \
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" mov r2, %0\n" \
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" mov r3, %1\n" \
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" .word %2\n" \
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" mov %0, r2" \
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: "+r"(temp) \
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: "r"(&v->counter), "i"(asm_op) \
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: "r2", "r3", "memory"); \
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\
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smp_mb(); \
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\
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return temp; \
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}
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op)
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
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#define atomic_sub(i, v) atomic_add(-(i), (v))
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#define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
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ATOMIC_OP(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
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#define atomic_andnot(mask, v) atomic_and(~(mask), (v))
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ATOMIC_OP(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
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ATOMIC_OP(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
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ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
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ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
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#endif /* CONFIG_ARC_PLAT_EZNPS */
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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@@ -15,8 +15,11 @@
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#define arch_spin_is_locked(x) ((x)->slock != __ARCH_SPIN_LOCK_UNLOCKED__)
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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#define arch_spin_unlock_wait(x) \
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do { while (arch_spin_is_locked(x)) cpu_relax(); } while (0)
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static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
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{
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smp_cond_load_acquire(&lock->slock, !VAL);
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}
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#ifdef CONFIG_ARC_HAS_LLSC
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