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[ARM] 3832/1: iop3xx: coding style cleanup

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Since the iop32x code isn't iop321-specific, and the iop33x code isn't
iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up
the code to conform to the coding style guidelines somewhat better.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lennert Buytenhek
2006-09-18 23:26:25 +01:00
committed by Russell King
parent 475549faa1
commit c852ac8044
41 changed files with 376 additions and 558 deletions
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95
arch/arm/mach-iop33x/irq.c
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@@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-iop33x/irq.c
* arch/arm/mach-iop33x/irq.c
*
* Generic IOP331 IRQ handling functionality
*
@@ -9,51 +9,44 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
static u32 iop331_mask0 = 0;
static u32 iop331_mask1 = 0;
static u32 iop33x_mask0;
static u32 iop33x_mask1;
static inline void intctl_write0(u32 val)
static inline void intctl0_write(u32 val)
{
// INTCTL0
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
}
static inline void intctl_write1(u32 val)
static inline void intctl1_write(u32 val)
{
// INTCTL1
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
}
static inline void intstr_write0(u32 val)
static inline void intstr0_write(u32 val)
{
// INTSTR0
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
}
static inline void intstr_write1(u32 val)
static inline void intstr1_write(u32 val)
{
// INTSTR1
iop3xx_cp6_enable();
asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
}
@@ -72,65 +65,63 @@ static inline void intsize_write(u32 val)
}
static void
iop331_irq_mask1 (unsigned int irq)
iop33x_irq_mask1 (unsigned int irq)
{
iop331_mask0 &= ~(1 << irq);
intctl_write0(iop331_mask0);
iop33x_mask0 &= ~(1 << irq);
intctl0_write(iop33x_mask0);
}
static void
iop331_irq_mask2 (unsigned int irq)
iop33x_irq_mask2 (unsigned int irq)
{
iop331_mask1 &= ~(1 << (irq - 32));
intctl_write1(iop331_mask1);
iop33x_mask1 &= ~(1 << (irq - 32));
intctl1_write(iop33x_mask1);
}
static void
iop331_irq_unmask1(unsigned int irq)
iop33x_irq_unmask1(unsigned int irq)
{
iop331_mask0 |= (1 << irq);
intctl_write0(iop331_mask0);
iop33x_mask0 |= 1 << irq;
intctl0_write(iop33x_mask0);
}
static void
iop331_irq_unmask2(unsigned int irq)
iop33x_irq_unmask2(unsigned int irq)
{
iop331_mask1 |= (1 << (irq - 32));
intctl_write1(iop331_mask1);
iop33x_mask1 |= (1 << (irq - 32));
intctl1_write(iop33x_mask1);
}
struct irq_chip iop331_irqchip1 = {
.name = "IOP-1",
.ack = iop331_irq_mask1,
.mask = iop331_irq_mask1,
.unmask = iop331_irq_unmask1,
struct irq_chip iop33x_irqchip1 = {
.name = "IOP33x-1",
.ack = iop33x_irq_mask1,
.mask = iop33x_irq_mask1,
.unmask = iop33x_irq_unmask1,
};
struct irq_chip iop331_irqchip2 = {
.name = "IOP-2",
.ack = iop331_irq_mask2,
.mask = iop331_irq_mask2,
.unmask = iop331_irq_unmask2,
struct irq_chip iop33x_irqchip2 = {
.name = "IOP33x-2",
.ack = iop33x_irq_mask2,
.mask = iop33x_irq_mask2,
.unmask = iop33x_irq_unmask2,
};
void __init iop331_init_irq(void)
void __init iop33x_init_irq(void)
{
unsigned int i;
int i;
intctl_write0(0); // disable all interrupts
intctl_write1(0);
intstr_write0(0); // treat all as IRQ
intstr_write1(0);
intctl0_write(0);
intctl1_write(0);
intstr0_write(0);
intstr1_write(0);
intbase_write(0);
intsize_write(1);
if(machine_is_iq80331()) // all interrupts are inputs to chip
if (machine_is_iq80331())
*IOP3XX_PCIIRSR = 0x0f;
for(i = 0; i < NR_IRQS; i++)
{
set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}