Merge branches 'fixes-for-linus', 'generic', 'cavium', 'module.h-fixes', 'next/ath79' and 'next/lantiq' into mips-for-linux-next
This commit is contained in:
Ralf Baechle
25
arch/mips/include/asm/clkdev.h
Normal file
25
arch/mips/include/asm/clkdev.h
Normal file
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* based on arch/arm/include/asm/clkdev.h
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||||
*
|
||||
* Copyright (C) 2008 Russell King.
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||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Helper for the clk API to assist looking up a struct clk.
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||||
*/
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||||
#ifndef __ASM_CLKDEV_H
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#define __ASM_CLKDEV_H
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#include <linux/slab.h>
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#define __clk_get(clk) ({ 1; })
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#define __clk_put(clk) do { } while (0)
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static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
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{
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return kzalloc(size, GFP_KERNEL);
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}
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||||
|
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#endif
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@@ -1,10 +1,11 @@
|
||||
/*
|
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* Atheros AR71XX/AR724X/AR913X SoC register definitions
|
||||
*
|
||||
* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
|
||||
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
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* Parts of this file are based on Atheros' 2.6.15 BSP
|
||||
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
@@ -60,6 +61,9 @@
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||||
#define AR933X_EHCI_BASE 0x1b000000
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#define AR933X_EHCI_SIZE 0x1000
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|
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#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR934X_WMAC_SIZE 0x20000
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||||
|
||||
/*
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* DDR_CTRL block
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*/
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@@ -91,6 +95,12 @@
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#define AR933X_DDR_REG_FLUSH_USB 0x84
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#define AR933X_DDR_REG_FLUSH_WMAC 0x88
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|
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#define AR934X_DDR_REG_FLUSH_GE0 0x9c
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#define AR934X_DDR_REG_FLUSH_GE1 0xa0
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#define AR934X_DDR_REG_FLUSH_USB 0xa4
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#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
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#define AR934X_DDR_REG_FLUSH_WMAC 0xac
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|
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/*
|
||||
* PLL block
|
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*/
|
||||
@@ -150,6 +160,41 @@
|
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
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|
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#define AR934X_PLL_CPU_CONFIG_REG 0x00
|
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#define AR934X_PLL_DDR_CONFIG_REG 0x04
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
|
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|
||||
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
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#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
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#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
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#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
|
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#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
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#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
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||||
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#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
|
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#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
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#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
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#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
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||||
#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
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#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
|
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#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
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#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
|
||||
|
||||
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
|
||||
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
|
||||
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
|
||||
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
|
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
|
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
|
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
|
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
|
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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|
||||
/*
|
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* USB_CONFIG block
|
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*/
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@@ -185,6 +230,10 @@
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#define AR933X_RESET_REG_RESET_MODULE 0x1c
|
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#define AR933X_RESET_REG_BOOTSTRAP 0xac
|
||||
|
||||
#define AR934X_RESET_REG_RESET_MODULE 0x1c
|
||||
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
||||
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
||||
|
||||
#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
|
||||
#define MISC_INT_TIMER3 BIT(9)
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@@ -241,6 +290,40 @@
|
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|
||||
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
|
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|
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
|
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#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
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#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
|
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#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
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#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
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#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
|
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#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
|
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#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
|
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#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
|
||||
#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
|
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#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
|
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#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
||||
#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
|
||||
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
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#define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
||||
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
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#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
|
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#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
|
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#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
|
||||
#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
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#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
|
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#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
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#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
|
||||
(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
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||||
AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
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||||
|
||||
#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
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(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
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||||
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
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AR934X_PCIE_WMAC_INT_PCIE_RC3)
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||||
|
||||
#define REV_ID_MAJOR_MASK 0xfff0
|
||||
#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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@@ -249,6 +332,9 @@
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#define REV_ID_MAJOR_AR7242 0x1100
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#define REV_ID_MAJOR_AR9330 0x0110
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#define REV_ID_MAJOR_AR9331 0x1110
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#define REV_ID_MAJOR_AR9341 0x0120
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#define REV_ID_MAJOR_AR9342 0x1120
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#define REV_ID_MAJOR_AR9344 0x2120
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#define AR71XX_REV_ID_MINOR_MASK 0x3
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#define AR71XX_REV_ID_MINOR_AR7130 0x0
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@@ -267,6 +353,8 @@
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||||
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#define AR724X_REV_ID_REVISION_MASK 0x3
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#define AR934X_REV_ID_REVISION_MASK 0xf
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/*
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* SPI block
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*/
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@@ -308,5 +396,6 @@
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#define AR724X_GPIO_COUNT 18
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#define AR913X_GPIO_COUNT 22
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#define AR933X_GPIO_COUNT 30
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#define AR934X_GPIO_COUNT 23
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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@@ -29,6 +29,9 @@ enum ath79_soc_type {
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ATH79_SOC_AR9132,
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ATH79_SOC_AR9330,
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ATH79_SOC_AR9331,
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ATH79_SOC_AR9341,
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ATH79_SOC_AR9342,
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ATH79_SOC_AR9344,
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};
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extern enum ath79_soc_type ath79_soc;
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@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void)
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ath79_soc == ATH79_SOC_AR9331);
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}
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static inline int soc_is_ar9341(void)
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{
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return (ath79_soc == ATH79_SOC_AR9341);
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}
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static inline int soc_is_ar9342(void)
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{
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return (ath79_soc == ATH79_SOC_AR9342);
|
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}
|
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static inline int soc_is_ar9344(void)
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{
|
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return (ath79_soc == ATH79_SOC_AR9344);
|
||||
}
|
||||
|
||||
static inline int soc_is_ar934x(void)
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{
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return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
||||
}
|
||||
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extern void __iomem *ath79_ddr_base;
|
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extern void __iomem *ath79_pll_base;
|
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extern void __iomem *ath79_reset_base;
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||||
|
||||
@@ -10,11 +10,19 @@
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||||
#define __ASM_MACH_ATH79_IRQ_H
|
||||
|
||||
#define MIPS_CPU_IRQ_BASE 0
|
||||
#define NR_IRQS 40
|
||||
#define NR_IRQS 48
|
||||
|
||||
#define ATH79_MISC_IRQ_BASE 8
|
||||
#define ATH79_MISC_IRQ_COUNT 32
|
||||
|
||||
#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
|
||||
#define ATH79_PCI_IRQ_COUNT 6
|
||||
#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
|
||||
|
||||
#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
|
||||
#define ATH79_IP2_IRQ_COUNT 2
|
||||
#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
|
||||
|
||||
#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
|
||||
#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
|
||||
#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
|
||||
|
||||
@@ -1,21 +0,0 @@
|
||||
/*
|
||||
* Atheros 724x PCI support
|
||||
*
|
||||
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
|
||||
#define __ASM_MACH_ATH79_PCI_ATH724X_H
|
||||
|
||||
struct ath724x_pci_data {
|
||||
int irq;
|
||||
void *pdata;
|
||||
};
|
||||
|
||||
void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
|
||||
|
||||
#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
|
||||
28
arch/mips/include/asm/mach-ath79/pci.h
Normal file
28
arch/mips/include/asm/mach-ath79/pci.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Atheros AR71XX/AR724X PCI support
|
||||
*
|
||||
* Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
||||
* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_ATH79_PCI_H
|
||||
#define __ASM_MACH_ATH79_PCI_H
|
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
|
||||
int ar71xx_pcibios_init(void);
|
||||
#else
|
||||
static inline int ar71xx_pcibios_init(void) { return 0; }
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_AR724X)
|
||||
int ar724x_pcibios_init(int irq);
|
||||
#else
|
||||
static inline int ar724x_pcibios_init(int irq) { return 0; }
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_ATH79_PCI_H */
|
||||
23
arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
Normal file
23
arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
|
||||
*/
|
||||
|
||||
#ifndef _FALCON_IRQ__
|
||||
#define _FALCON_IRQ__
|
||||
|
||||
#define INT_NUM_IRQ0 8
|
||||
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
|
||||
#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
|
||||
#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
|
||||
#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
|
||||
#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
|
||||
#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
|
||||
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
|
||||
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
||||
|
||||
#endif /* _FALCON_IRQ__ */
|
||||
18
arch/mips/include/asm/mach-lantiq/falcon/irq.h
Normal file
18
arch/mips/include/asm/mach-lantiq/falcon/irq.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
|
||||
*/
|
||||
|
||||
#ifndef __FALCON_IRQ_H
|
||||
#define __FALCON_IRQ_H
|
||||
|
||||
#include <falcon_irq.h>
|
||||
|
||||
#define NR_IRQS 328
|
||||
|
||||
#include_next <irq.h>
|
||||
|
||||
#endif
|
||||
67
arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
Normal file
67
arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _LTQ_FALCON_H__
|
||||
#define _LTQ_FALCON_H__
|
||||
|
||||
#ifdef CONFIG_SOC_FALCON
|
||||
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <lantiq.h>
|
||||
|
||||
/* Chip IDs */
|
||||
#define SOC_ID_FALCON 0x01B8
|
||||
|
||||
/* SoC Types */
|
||||
#define SOC_TYPE_FALCON 0x01
|
||||
|
||||
/*
|
||||
* during early_printk no ioremap possible at this early stage
|
||||
* lets use KSEG1 instead
|
||||
*/
|
||||
#define LTQ_ASC0_BASE_ADDR 0x1E100C00
|
||||
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
|
||||
|
||||
/* WDT */
|
||||
#define LTQ_RST_CAUSE_WDTRST 0x0002
|
||||
|
||||
/* CHIP ID */
|
||||
#define LTQ_STATUS_BASE_ADDR 0x1E802000
|
||||
|
||||
#define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
|
||||
#define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
|
||||
#define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
|
||||
|
||||
/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
|
||||
#define SYSCTL_SYS1 0
|
||||
#define SYSCTL_SYSETH 1
|
||||
#define SYSCTL_SYSGPE 2
|
||||
|
||||
/* BOOT_SEL - find what boot media we have */
|
||||
#define BS_FLASH 0x1
|
||||
#define BS_SPI 0x4
|
||||
|
||||
/* global register ranges */
|
||||
extern __iomem void *ltq_ebu_membase;
|
||||
extern __iomem void *ltq_sys1_membase;
|
||||
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
|
||||
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
|
||||
|
||||
#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
|
||||
#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
|
||||
#define ltq_sys1_w32_mask(clear, set, reg) \
|
||||
ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
|
||||
|
||||
/*
|
||||
* to keep the irq code generic we need to define this to 0 as falcon
|
||||
* has no EIU/EBU
|
||||
*/
|
||||
#define LTQ_EBU_PCC_ISTAT 0
|
||||
|
||||
#endif /* CONFIG_SOC_FALCON */
|
||||
#endif /* _LTQ_XWAY_H__ */
|
||||
16
arch/mips/include/asm/mach-lantiq/gpio.h
Normal file
16
arch/mips/include/asm/mach-lantiq/gpio.h
Normal file
@@ -0,0 +1,16 @@
|
||||
#ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H
|
||||
#define __ASM_MIPS_MACH_LANTIQ_GPIO_H
|
||||
|
||||
static inline int gpio_to_irq(unsigned int gpio)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
#define gpio_get_value __gpio_get_value
|
||||
#define gpio_set_value __gpio_set_value
|
||||
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif
|
||||
@@ -9,6 +9,8 @@
|
||||
#define _LANTIQ_H__
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
/* generic reg access functions */
|
||||
#define ltq_r32(reg) __raw_readl(reg)
|
||||
@@ -21,25 +23,9 @@
|
||||
/* register access macros for EBU and CGU */
|
||||
#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
|
||||
#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
|
||||
#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
|
||||
#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
|
||||
|
||||
#define ltq_ebu_w32_mask(x, y, z) \
|
||||
ltq_w32_mask(x, y, ltq_ebu_membase + (z))
|
||||
extern __iomem void *ltq_ebu_membase;
|
||||
extern __iomem void *ltq_cgu_membase;
|
||||
|
||||
extern unsigned int ltq_get_cpu_ver(void);
|
||||
extern unsigned int ltq_get_soc_type(void);
|
||||
|
||||
/* clock speeds */
|
||||
#define CLOCK_60M 60000000
|
||||
#define CLOCK_83M 83333333
|
||||
#define CLOCK_111M 111111111
|
||||
#define CLOCK_133M 133333333
|
||||
#define CLOCK_167M 166666667
|
||||
#define CLOCK_200M 200000000
|
||||
#define CLOCK_266M 266666666
|
||||
#define CLOCK_333M 333333333
|
||||
#define CLOCK_400M 400000000
|
||||
|
||||
/* spinlock all ebu i/o */
|
||||
extern spinlock_t ebu_lock;
|
||||
@@ -49,15 +35,21 @@ extern void ltq_disable_irq(struct irq_data *data);
|
||||
extern void ltq_mask_and_ack_irq(struct irq_data *data);
|
||||
extern void ltq_enable_irq(struct irq_data *data);
|
||||
|
||||
/* clock handling */
|
||||
extern int clk_activate(struct clk *clk);
|
||||
extern void clk_deactivate(struct clk *clk);
|
||||
extern struct clk *clk_get_cpu(void);
|
||||
extern struct clk *clk_get_fpi(void);
|
||||
extern struct clk *clk_get_io(void);
|
||||
|
||||
/* find out what bootsource we have */
|
||||
extern unsigned char ltq_boot_select(void);
|
||||
/* find out what caused the last cpu reset */
|
||||
extern int ltq_reset_cause(void);
|
||||
#define LTQ_RST_CAUSE_WDTRST 0x20
|
||||
|
||||
#define IOPORT_RESOURCE_START 0x10000000
|
||||
#define IOPORT_RESOURCE_END 0xffffffff
|
||||
#define IOMEM_RESOURCE_START 0x10000000
|
||||
#define IOMEM_RESOURCE_END 0xffffffff
|
||||
#define LTQ_FLASH_START 0x10000000
|
||||
#define LTQ_FLASH_MAX 0x04000000
|
||||
|
||||
#endif
|
||||
|
||||
@@ -9,41 +9,8 @@
|
||||
#ifndef _LANTIQ_PLATFORM_H__
|
||||
#define _LANTIQ_PLATFORM_H__
|
||||
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/socket.h>
|
||||
|
||||
/* struct used to pass info to the pci core */
|
||||
enum {
|
||||
PCI_CLOCK_INT = 0,
|
||||
PCI_CLOCK_EXT
|
||||
};
|
||||
|
||||
#define PCI_EXIN0 0x0001
|
||||
#define PCI_EXIN1 0x0002
|
||||
#define PCI_EXIN2 0x0004
|
||||
#define PCI_EXIN3 0x0008
|
||||
#define PCI_EXIN4 0x0010
|
||||
#define PCI_EXIN5 0x0020
|
||||
#define PCI_EXIN_MAX 6
|
||||
|
||||
#define PCI_GNT1 0x0040
|
||||
#define PCI_GNT2 0x0080
|
||||
#define PCI_GNT3 0x0100
|
||||
#define PCI_GNT4 0x0200
|
||||
|
||||
#define PCI_REQ1 0x0400
|
||||
#define PCI_REQ2 0x0800
|
||||
#define PCI_REQ3 0x1000
|
||||
#define PCI_REQ4 0x2000
|
||||
#define PCI_REQ_SHIFT 10
|
||||
#define PCI_REQ_MASK 0xf
|
||||
|
||||
struct ltq_pci_data {
|
||||
int clock;
|
||||
int gpio;
|
||||
int irq[16];
|
||||
};
|
||||
|
||||
/* struct used to pass info to network drivers */
|
||||
struct ltq_eth_data {
|
||||
struct sockaddr mac;
|
||||
|
||||
@@ -17,50 +17,8 @@
|
||||
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
|
||||
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
|
||||
|
||||
#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
|
||||
#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
|
||||
#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
|
||||
|
||||
#define LTQ_ASC_ASE_TIR INT_NUM_IM2_IRL0
|
||||
#define LTQ_ASC_ASE_RIR (INT_NUM_IM2_IRL0 + 2)
|
||||
#define LTQ_ASC_ASE_EIR (INT_NUM_IM2_IRL0 + 3)
|
||||
|
||||
#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
|
||||
#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
|
||||
#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
|
||||
|
||||
#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
|
||||
#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
|
||||
|
||||
#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
|
||||
#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
|
||||
#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
|
||||
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
||||
|
||||
#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
|
||||
#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
|
||||
#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
|
||||
#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
|
||||
#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
|
||||
#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
|
||||
#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
|
||||
#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
|
||||
#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
|
||||
#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
|
||||
#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
|
||||
#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
|
||||
#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
|
||||
#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
|
||||
#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
|
||||
#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
|
||||
#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
|
||||
#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
|
||||
#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
|
||||
#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
|
||||
|
||||
#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
|
||||
|
||||
#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
|
||||
#define MIPS_CPU_TIMER_IRQ 7
|
||||
|
||||
#endif
|
||||
|
||||
@@ -17,38 +17,56 @@
|
||||
#define SOC_ID_DANUBE1 0x129
|
||||
#define SOC_ID_DANUBE2 0x12B
|
||||
#define SOC_ID_TWINPASS 0x12D
|
||||
#define SOC_ID_AMAZON_SE 0x152
|
||||
#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
|
||||
#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
|
||||
#define SOC_ID_ARX188 0x16C
|
||||
#define SOC_ID_ARX168 0x16D
|
||||
#define SOC_ID_ARX168_1 0x16D
|
||||
#define SOC_ID_ARX168_2 0x16E
|
||||
#define SOC_ID_ARX182 0x16F
|
||||
#define SOC_ID_GRX188 0x170
|
||||
#define SOC_ID_GRX168 0x171
|
||||
|
||||
/* SoC Types */
|
||||
#define SOC_ID_VRX288 0x1C0 /* v1.1 */
|
||||
#define SOC_ID_VRX282 0x1C1 /* v1.1 */
|
||||
#define SOC_ID_VRX268 0x1C2 /* v1.1 */
|
||||
#define SOC_ID_GRX268 0x1C8 /* v1.1 */
|
||||
#define SOC_ID_GRX288 0x1C9 /* v1.1 */
|
||||
#define SOC_ID_VRX288_2 0x00B /* v1.2 */
|
||||
#define SOC_ID_VRX268_2 0x00C /* v1.2 */
|
||||
#define SOC_ID_GRX288_2 0x00D /* v1.2 */
|
||||
#define SOC_ID_GRX282_2 0x00E /* v1.2 */
|
||||
|
||||
/* SoC Types */
|
||||
#define SOC_TYPE_DANUBE 0x01
|
||||
#define SOC_TYPE_TWINPASS 0x02
|
||||
#define SOC_TYPE_AR9 0x03
|
||||
#define SOC_TYPE_VR9 0x04
|
||||
#define SOC_TYPE_AMAZON_SE 0x05
|
||||
#define SOC_TYPE_VR9 0x04 /* v1.1 */
|
||||
#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
|
||||
#define SOC_TYPE_AMAZON_SE 0x06
|
||||
|
||||
/* ASC0/1 - serial port */
|
||||
#define LTQ_ASC0_BASE_ADDR 0x1E100400
|
||||
/* BOOT_SEL - find what boot media we have */
|
||||
#define BS_EXT_ROM 0x0
|
||||
#define BS_FLASH 0x1
|
||||
#define BS_MII0 0x2
|
||||
#define BS_PCI 0x3
|
||||
#define BS_UART1 0x4
|
||||
#define BS_SPI 0x5
|
||||
#define BS_NAND 0x6
|
||||
#define BS_RMII0 0x7
|
||||
|
||||
/* helpers used to access the cgu */
|
||||
#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
|
||||
#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
|
||||
extern __iomem void *ltq_cgu_membase;
|
||||
|
||||
/*
|
||||
* during early_printk no ioremap is possible
|
||||
* lets use KSEG1 instead
|
||||
*/
|
||||
#define LTQ_ASC1_BASE_ADDR 0x1E100C00
|
||||
#define LTQ_ASC_SIZE 0x400
|
||||
|
||||
/* RCU - reset control unit */
|
||||
#define LTQ_RCU_BASE_ADDR 0x1F203000
|
||||
#define LTQ_RCU_SIZE 0x1000
|
||||
|
||||
/* GPTU - general purpose timer unit */
|
||||
#define LTQ_GPTU_BASE_ADDR 0x18000300
|
||||
#define LTQ_GPTU_SIZE 0x100
|
||||
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
|
||||
|
||||
/* EBU - external bus unit */
|
||||
#define LTQ_EBU_GPIO_START 0x14000000
|
||||
#define LTQ_EBU_GPIO_SIZE 0x1000
|
||||
|
||||
#define LTQ_EBU_BASE_ADDR 0x1E105300
|
||||
#define LTQ_EBU_SIZE 0x100
|
||||
|
||||
#define LTQ_EBU_BUSCON0 0x0060
|
||||
#define LTQ_EBU_PCC_CON 0x0090
|
||||
#define LTQ_EBU_PCC_IEN 0x00A4
|
||||
@@ -57,85 +75,17 @@
|
||||
#define LTQ_EBU_ADDRSEL1 0x0024
|
||||
#define EBU_WRDIS 0x80000000
|
||||
|
||||
/* CGU - clock generation unit */
|
||||
#define LTQ_CGU_BASE_ADDR 0x1F103000
|
||||
#define LTQ_CGU_SIZE 0x1000
|
||||
|
||||
/* ICU - interrupt control unit */
|
||||
#define LTQ_ICU_BASE_ADDR 0x1F880200
|
||||
#define LTQ_ICU_SIZE 0x100
|
||||
|
||||
/* EIU - external interrupt unit */
|
||||
#define LTQ_EIU_BASE_ADDR 0x1F101000
|
||||
#define LTQ_EIU_SIZE 0x1000
|
||||
|
||||
/* PMU - power management unit */
|
||||
#define LTQ_PMU_BASE_ADDR 0x1F102000
|
||||
#define LTQ_PMU_SIZE 0x1000
|
||||
|
||||
#define PMU_DMA 0x0020
|
||||
#define PMU_USB 0x8041
|
||||
#define PMU_LED 0x0800
|
||||
#define PMU_GPT 0x1000
|
||||
#define PMU_PPE 0x2000
|
||||
#define PMU_FPI 0x4000
|
||||
#define PMU_SWITCH 0x10000000
|
||||
|
||||
/* ETOP - ethernet */
|
||||
#define LTQ_ETOP_BASE_ADDR 0x1E180000
|
||||
#define LTQ_ETOP_SIZE 0x40000
|
||||
|
||||
/* DMA */
|
||||
#define LTQ_DMA_BASE_ADDR 0x1E104100
|
||||
#define LTQ_DMA_SIZE 0x800
|
||||
|
||||
/* PCI */
|
||||
#define PCI_CR_BASE_ADDR 0x1E105400
|
||||
#define PCI_CR_SIZE 0x400
|
||||
|
||||
/* WDT */
|
||||
#define LTQ_WDT_BASE_ADDR 0x1F8803F0
|
||||
#define LTQ_WDT_SIZE 0x10
|
||||
|
||||
/* STP - serial to parallel conversion unit */
|
||||
#define LTQ_STP_BASE_ADDR 0x1E100BB0
|
||||
#define LTQ_STP_SIZE 0x40
|
||||
|
||||
/* GPIO */
|
||||
#define LTQ_GPIO0_BASE_ADDR 0x1E100B10
|
||||
#define LTQ_GPIO1_BASE_ADDR 0x1E100B40
|
||||
#define LTQ_GPIO2_BASE_ADDR 0x1E100B70
|
||||
#define LTQ_GPIO_SIZE 0x30
|
||||
|
||||
/* SSC */
|
||||
#define LTQ_SSC_BASE_ADDR 0x1e100800
|
||||
#define LTQ_SSC_SIZE 0x100
|
||||
|
||||
/* MEI - dsl core */
|
||||
#define LTQ_MEI_BASE_ADDR 0x1E116000
|
||||
|
||||
/* DEU - data encryption unit */
|
||||
#define LTQ_DEU_BASE_ADDR 0x1E103100
|
||||
#define LTQ_RST_CAUSE_WDTRST 0x20
|
||||
|
||||
/* MPS - multi processor unit (voice) */
|
||||
#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
|
||||
#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
|
||||
|
||||
/* request a non-gpio and set the PIO config */
|
||||
extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
|
||||
unsigned int alt1, unsigned int dir, const char *name);
|
||||
#define PMU_PPE BIT(13)
|
||||
extern void ltq_pmu_enable(unsigned int module);
|
||||
extern void ltq_pmu_disable(unsigned int module);
|
||||
|
||||
static inline int ltq_is_ar9(void)
|
||||
{
|
||||
return (ltq_get_soc_type() == SOC_TYPE_AR9);
|
||||
}
|
||||
|
||||
static inline int ltq_is_vr9(void)
|
||||
{
|
||||
return (ltq_get_soc_type() == SOC_TYPE_VR9);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SOC_TYPE_XWAY */
|
||||
#endif /* _LTQ_XWAY_H__ */
|
||||
|
||||
@@ -93,8 +93,4 @@ extern void mips_pcibios_init(void);
|
||||
#define mips_pcibios_init() do { } while (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
extern void kgdb_config(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
#define _ASM_MODULE_H
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <linux/elf.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
struct mod_arch_specific {
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
/*
|
||||
* Each pci channel is a top-level PCI bus seem by CPU. A machine with
|
||||
@@ -26,6 +27,7 @@
|
||||
struct pci_controller {
|
||||
struct pci_controller *next;
|
||||
struct pci_bus *bus;
|
||||
struct device_node *of_node;
|
||||
|
||||
struct pci_ops *pci_ops;
|
||||
struct resource *mem_resource;
|
||||
@@ -142,4 +144,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
|
||||
|
||||
extern char * (*pcibios_plat_setup)(char *str);
|
||||
|
||||
/* this function parses memory ranges from a device node */
|
||||
extern void __devinit pci_load_of_ranges(struct pci_controller *hose,
|
||||
struct device_node *node);
|
||||
|
||||
#endif /* _ASM_PCI_H */
|
||||
|
||||
@@ -12,6 +12,9 @@
|
||||
#define __ASM_PROM_H
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
#include <linux/bug.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
extern int early_init_dt_scan_memory_arch(unsigned long node,
|
||||
@@ -21,6 +24,29 @@ extern int reserve_mem_mach(unsigned long addr, unsigned long size);
|
||||
extern void free_mem_mach(unsigned long addr, unsigned long size);
|
||||
|
||||
extern void device_tree_init(void);
|
||||
|
||||
static inline unsigned long pci_address_to_pio(phys_addr_t address)
|
||||
{
|
||||
/*
|
||||
* The ioport address can be directly used by inX() / outX()
|
||||
*/
|
||||
BUG_ON(address > IO_SPACE_LIMIT);
|
||||
|
||||
return (unsigned long) address;
|
||||
}
|
||||
#define pci_address_to_pio pci_address_to_pio
|
||||
|
||||
struct boot_param_header;
|
||||
|
||||
extern void __dt_setup_arch(struct boot_param_header *bph);
|
||||
|
||||
#define dt_setup_arch(sym) \
|
||||
({ \
|
||||
extern struct boot_param_header __dtb_##sym##_begin; \
|
||||
\
|
||||
__dt_setup_arch(&__dtb_##sym##_begin); \
|
||||
})
|
||||
|
||||
#else /* CONFIG_OF */
|
||||
static inline void device_tree_init(void) { }
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
@@ -14,7 +14,8 @@ extern void *set_vi_handler(int n, vi_handler_t addr);
|
||||
|
||||
extern void *set_except_vector(int n, void *addr);
|
||||
extern unsigned long ebase;
|
||||
extern void per_cpu_trap_init(void);
|
||||
extern void per_cpu_trap_init(bool);
|
||||
extern void cpu_cache_init(void);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
|
||||
@@ -60,7 +60,7 @@ struct termio {
|
||||
};
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <linux/module.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
/*
|
||||
* intr=^C quit=^\ erase=del kill=^U
|
||||
|
||||
@@ -25,6 +25,7 @@ extern void (*board_nmi_handler_setup)(void);
|
||||
extern void (*board_ejtag_handler_setup)(void);
|
||||
extern void (*board_bind_eic_interrupt)(int irq, int regset);
|
||||
extern void (*board_ebase_setup)(void);
|
||||
extern void (*board_cache_error_setup)(void);
|
||||
|
||||
extern int register_nmi_notifier(struct notifier_block *nb);
|
||||
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
#include <linux/types.h>
|
||||
|
||||
#ifdef CONFIG_EXPORT_UASM
|
||||
#include <linux/module.h>
|
||||
#include <linux/export.h>
|
||||
#define __uasminit
|
||||
#define __uasminitdata
|
||||
#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
|
||||
|
||||
Reference in New Issue
Block a user