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drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation

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Roy Spliet:
- Implement according to specs
- Simplify
- Make array for mc latency registers

Martin Peres:
- squash and split all the commits from Roy
- rework following Ben Skeggs comments
- add a form of timings validation
- store the initial timings for later use

Ben Skeggs
- merge slightly modified tidy-up patch with this one
- remove perflvl-dropping logic for the moment

Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Roy Spliet
2012-01-09 15:23:07 +10:00
committed by Ben Skeggs
parent 03ddf04bdb
commit c7c039fd31
4 changed files with 474 additions and 150 deletions
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1
drivers/gpu/drm/nouveau/nouveau_pm.c
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@@ -808,6 +808,7 @@ nouveau_pm_init(struct drm_device *dev)
ret = nouveau_pm_perflvl_get(dev, &pm->boot);
if (ret == 0) {
strncpy(pm->boot.name, "boot", 4);
pm->boot.timing = &pm->memtimings.boot;
pm->cur = &pm->boot;
nouveau_pm_perflvl_info(&pm->boot, info, sizeof(info));