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clk: meson: add gp0 frac parameter for axg and gxl

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Add the frac parameter for the gp0 pll of the axg and gxl.
This allows to achieve rates between the fixed settings provided
by the table.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Jerome Brunet
2018-02-19 12:21:40 +01:00
committed by Neil Armstrong
parent 8289aafa4f
commit c77de0e5c9
2 changed files with 12 additions and 2 deletions
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7
drivers/clk/meson/axg.c
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@@ -193,7 +193,7 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
};
const struct reg_sequence axg_gp0_init_regs[] = {
{ .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 },
{ .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
@@ -218,6 +218,11 @@ static struct clk_regmap axg_gp0_pll = {
.shift = 16,
.width = 2,
},
.frac = {
.reg_off = HHI_GP0_PLL_CNTL1,
.shift = 0,
.width = 10,
},
.l = {
.reg_off = HHI_GP0_PLL_CNTL,
.shift = 31,