irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers
Most implementations of the bcm7120-l2 controller only have a single 32-bit enable word + 32-bit status word. But some instances have added more enable/status pairs in order to support 64+ IRQs (which are all ORed into one parent IRQ input). Make the following changes to allow the driver to support this: - Extend DT bindings so that multiple words can be specified for the reg property, various masks, etc. - Add loops to the probe/handle functions to deal with each word separately - Allocate 1 generic-chip for every 32 IRQs, so we can still use the clr/set helper functions - Update the documentation This uses one domain per bcm7120-l2 DT node. If the DT node defines multiple enable/status pairs (i.e. >=64 IRQs) then the driver will create a single IRQ domain with 2+ generic chips. Multiple generic chips are required because the generic-chip code can only handle one enable/status register pair per instance. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/1415342669-30640-12-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Kevin Cernekee
@@ -23,6 +23,7 @@
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/reboot.h>
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#include <linux/bitops.h>
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#include <linux/irqchip/chained_irq.h>
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#include "irqchip.h"
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@@ -31,27 +32,42 @@
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#define IRQEN 0x00
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#define IRQSTAT 0x04
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#define MAX_WORDS 4
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#define IRQS_PER_WORD 32
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struct bcm7120_l2_intc_data {
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void __iomem *base;
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unsigned int n_words;
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void __iomem *base[MAX_WORDS];
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struct irq_domain *domain;
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bool can_wake;
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u32 irq_fwd_mask;
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u32 irq_map_mask;
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u32 irq_fwd_mask[MAX_WORDS];
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u32 irq_map_mask[MAX_WORDS];
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};
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static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
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{
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struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 status;
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unsigned int idx;
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chained_irq_enter(chip, desc);
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status = __raw_readl(b->base + IRQSTAT);
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while (status) {
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irq = ffs(status) - 1;
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status &= ~(1 << irq);
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generic_handle_irq(irq_find_mapping(b->domain, irq));
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for (idx = 0; idx < b->n_words; idx++) {
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int base = idx * IRQS_PER_WORD;
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struct irq_chip_generic *gc =
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irq_get_domain_generic_chip(b->domain, base);
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unsigned long pending;
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int hwirq;
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irq_gc_lock(gc);
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pending = __raw_readl(b->base[idx] + IRQSTAT) &
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gc->mask_cache;
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irq_gc_unlock(gc);
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for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
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generic_handle_irq(irq_find_mapping(b->domain,
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base + hwirq));
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}
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}
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chained_irq_exit(chip, desc);
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@@ -65,7 +81,7 @@ static void bcm7120_l2_intc_suspend(struct irq_data *d)
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irq_gc_lock(gc);
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if (b->can_wake) {
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__raw_writel(gc->mask_cache | gc->wake_active,
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b->base + IRQEN);
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gc->reg_base + IRQEN);
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}
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irq_gc_unlock(gc);
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}
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@@ -76,7 +92,7 @@ static void bcm7120_l2_intc_resume(struct irq_data *d)
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/* Restore the saved mask */
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irq_gc_lock(gc);
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__raw_writel(gc->mask_cache, b->base + IRQEN);
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__raw_writel(gc->mask_cache, gc->reg_base + IRQEN);
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irq_gc_unlock(gc);
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}
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@@ -85,6 +101,7 @@ static int bcm7120_l2_intc_init_one(struct device_node *dn,
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int irq, const __be32 *map_mask)
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{
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int parent_irq;
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unsigned int idx;
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parent_irq = irq_of_parse_and_map(dn, irq);
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if (parent_irq < 0) {
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@@ -92,7 +109,12 @@ static int bcm7120_l2_intc_init_one(struct device_node *dn,
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return parent_irq;
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}
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data->irq_map_mask |= be32_to_cpup(map_mask + irq);
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/* For multiple parent IRQs with multiple words, this looks like:
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* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
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*/
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for (idx = 0; idx < data->n_words; idx++)
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data->irq_map_mask[idx] |=
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be32_to_cpup(map_mask + irq * data->n_words + idx);
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irq_set_handler_data(parent_irq, data);
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irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);
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@@ -109,26 +131,41 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn,
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struct irq_chip_type *ct;
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const __be32 *map_mask;
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int num_parent_irqs;
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int ret = 0, len, irq;
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int ret = 0, len;
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unsigned int idx, irq;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->base = of_iomap(dn, 0);
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if (!data->base) {
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for (idx = 0; idx < MAX_WORDS; idx++) {
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data->base[idx] = of_iomap(dn, idx);
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if (!data->base[idx])
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break;
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data->n_words = idx + 1;
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}
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if (!data->n_words) {
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pr_err("failed to remap intc L2 registers\n");
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ret = -ENOMEM;
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goto out_free;
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goto out_unmap;
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}
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if (of_property_read_u32(dn, "brcm,int-fwd-mask", &data->irq_fwd_mask))
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data->irq_fwd_mask = 0;
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/* Enable all interrupt specified in the interrupt forward mask and have
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* the other disabled
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/* Enable all interrupts specified in the interrupt forward mask;
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* disable all others. If the property doesn't exist (-EINVAL),
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* assume all zeroes.
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*/
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__raw_writel(data->irq_fwd_mask, data->base + IRQEN);
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ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
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data->irq_fwd_mask, data->n_words);
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if (ret == 0 || ret == -EINVAL) {
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for (idx = 0; idx < data->n_words; idx++)
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__raw_writel(data->irq_fwd_mask[idx],
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data->base[idx] + IRQEN);
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} else {
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/* property exists but has the wrong number of words */
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pr_err("invalid int-fwd-mask property\n");
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ret = -EINVAL;
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goto out_unmap;
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}
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num_parent_irqs = of_irq_count(dn);
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if (num_parent_irqs <= 0) {
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@@ -138,7 +175,8 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn,
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}
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map_mask = of_get_property(dn, "brcm,int-map-mask", &len);
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if (!map_mask || (len != (sizeof(*map_mask) * num_parent_irqs))) {
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if (!map_mask ||
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(len != (sizeof(*map_mask) * num_parent_irqs * data->n_words))) {
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pr_err("invalid brcm,int-map-mask property\n");
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ret = -EINVAL;
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goto out_unmap;
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@@ -150,14 +188,14 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn,
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goto out_unmap;
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}
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data->domain = irq_domain_add_linear(dn, 32,
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&irq_generic_chip_ops, NULL);
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data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
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&irq_generic_chip_ops, NULL);
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if (!data->domain) {
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ret = -ENOMEM;
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goto out_unmap;
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}
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ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
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ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
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dn->full_name, handle_level_irq, clr, 0,
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IRQ_GC_INIT_MASK_CACHE);
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if (ret) {
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@@ -165,39 +203,47 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn,
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goto out_free_domain;
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}
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gc = irq_get_domain_generic_chip(data->domain, 0);
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gc->unused = 0xffffffff & ~data->irq_map_mask;
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gc->reg_base = data->base;
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gc->private = data;
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ct = gc->chip_types;
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ct->regs.mask = IRQEN;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_ack = irq_gc_noop;
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ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
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ct->chip.irq_resume = bcm7120_l2_intc_resume;
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if (of_property_read_bool(dn, "brcm,irq-can-wake")) {
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if (of_property_read_bool(dn, "brcm,irq-can-wake"))
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data->can_wake = true;
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/* This IRQ chip can wake the system, set all relevant child
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* interupts in wake_enabled mask
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*/
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gc->wake_enabled = 0xffffffff;
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gc->wake_enabled &= ~gc->unused;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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for (idx = 0; idx < data->n_words; idx++) {
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irq = idx * IRQS_PER_WORD;
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gc = irq_get_domain_generic_chip(data->domain, irq);
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gc->unused = 0xffffffff & ~data->irq_map_mask[idx];
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gc->reg_base = data->base[idx];
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gc->private = data;
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ct = gc->chip_types;
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ct->regs.mask = IRQEN;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_ack = irq_gc_noop;
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ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
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ct->chip.irq_resume = bcm7120_l2_intc_resume;
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if (data->can_wake) {
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/* This IRQ chip can wake the system, set all
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* relevant child interupts in wake_enabled mask
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*/
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gc->wake_enabled = 0xffffffff;
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gc->wake_enabled &= ~gc->unused;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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}
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}
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pr_info("registered BCM7120 L2 intc (mem: 0x%p, parent IRQ(s): %d)\n",
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data->base, num_parent_irqs);
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data->base[0], num_parent_irqs);
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return 0;
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out_free_domain:
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irq_domain_remove(data->domain);
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out_unmap:
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iounmap(data->base);
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out_free:
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for (idx = 0; idx < MAX_WORDS; idx++) {
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if (data->base[idx])
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iounmap(data->base[idx]);
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}
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kfree(data);
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return ret;
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}
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