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Merge drm/drm-next into drm-intel-next-queued

Browse Source 
We need a backmerge to get DP_DPCD_REV_14 before we push other
i915 changes to dinq that could break compilation.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Rodrigo Vivi
2018-07-23 09:13:12 -07:00
parent 6f15a7de86 500775074f
commit c74a7469f9
13380 changed files with 538236 additions and 634893 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
include/acpi/acnames.h
View File

@@ -49,11 +49,14 @@
/* Definitions of the predefined namespace names */
#define ACPI_UNKNOWN_NAME (u32) 0x3F3F3F3F /* Unknown name is "????" */
#define ACPI_ROOT_NAME (u32) 0x5F5F5F5C /* Root name is "\___" */
#define ACPI_PREFIX_MIXED (u32) 0x69706341 /* "Acpi" */
#define ACPI_PREFIX_LOWER (u32) 0x69706361 /* "acpi" */
/* Root name stuff */
#define ACPI_ROOT_NAME (u32) 0x5F5F5F5C /* Root name is "\___" */
#define ACPI_ROOT_PATHNAME "\\___"
#define ACPI_NAMESPACE_ROOT "Namespace Root"
#define ACPI_NS_ROOT_PATH "\\"
#endif /* __ACNAMES_H__ */

4
include/acpi/acoutput.h
View File

@@ -80,7 +80,8 @@
#define ACPI_LV_ALLOCATIONS 0x00100000
#define ACPI_LV_FUNCTIONS 0x00200000
#define ACPI_LV_OPTIMIZATIONS 0x00400000
#define ACPI_LV_VERBOSITY2 0x00700000 | ACPI_LV_VERBOSITY1
#define ACPI_LV_PARSE_TREES 0x00800000
#define ACPI_LV_VERBOSITY2 0x00F00000 | ACPI_LV_VERBOSITY1
#define ACPI_LV_ALL ACPI_LV_VERBOSITY2
/* Trace verbosity level 3 [Threading, I/O, and Interrupts] */
@@ -131,6 +132,7 @@
#define ACPI_DB_TABLES ACPI_DEBUG_LEVEL (ACPI_LV_TABLES)
#define ACPI_DB_FUNCTIONS ACPI_DEBUG_LEVEL (ACPI_LV_FUNCTIONS)
#define ACPI_DB_OPTIMIZATIONS ACPI_DEBUG_LEVEL (ACPI_LV_OPTIMIZATIONS)
#define ACPI_DB_PARSE_TREES ACPI_DEBUG_LEVEL (ACPI_LV_PARSE_TREES)
#define ACPI_DB_VALUES ACPI_DEBUG_LEVEL (ACPI_LV_VALUES)
#define ACPI_DB_OBJECTS ACPI_DEBUG_LEVEL (ACPI_LV_OBJECTS)
#define ACPI_DB_ALLOCATIONS ACPI_DEBUG_LEVEL (ACPI_LV_ALLOCATIONS)

21
include/acpi/acpiosxf.h
View File

@@ -97,6 +97,27 @@ acpi_cpu_flags acpi_os_acquire_lock(acpi_spinlock handle);
void acpi_os_release_lock(acpi_spinlock handle, acpi_cpu_flags flags);
#endif
/*
* RAW spinlock primitives. If the OS does not provide them, fallback to
* spinlock primitives
*/
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_create_raw_lock
# define acpi_os_create_raw_lock(out_handle) acpi_os_create_lock(out_handle)
#endif
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_delete_raw_lock
# define acpi_os_delete_raw_lock(handle) acpi_os_delete_lock(handle)
#endif
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_acquire_raw_lock
# define acpi_os_acquire_raw_lock(handle) acpi_os_acquire_lock(handle)
#endif
#ifndef ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_release_raw_lock
# define acpi_os_release_raw_lock(handle, flags) \
acpi_os_release_lock(handle, flags)
#endif
/*
* Semaphore primitives
*/

3
include/acpi/acpixf.h
View File

@@ -12,7 +12,7 @@
/* Current ACPICA subsystem version in YYYYMMDD format */
#define ACPI_CA_VERSION 0x20180313
#define ACPI_CA_VERSION 0x20180531
#include <acpi/acconfig.h>
#include <acpi/actypes.h>
@@ -753,6 +753,7 @@ ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status
u32 gpe_number,
acpi_event_status
*event_status))
ACPI_HW_DEPENDENT_RETURN_VOID(void acpi_dispatch_gpe(acpi_handle gpe_device, u32 gpe_number))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_disable_all_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_enable_all_runtime_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_enable_all_wakeup_gpes(void))

25
include/acpi/actbl2.h
View File

@@ -67,7 +67,7 @@
* IORT - IO Remapping Table
*
* Conforms to "IO Remapping Table System Software on ARM Platforms",
* Document number: ARM DEN 0049C, May 2017
* Document number: ARM DEN 0049D, March 2018
*
******************************************************************************/
@@ -98,7 +98,8 @@ enum acpi_iort_node_type {
ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
ACPI_IORT_NODE_SMMU = 0x03,
ACPI_IORT_NODE_SMMU_V3 = 0x04
ACPI_IORT_NODE_SMMU_V3 = 0x04,
ACPI_IORT_NODE_PMCG = 0x05
};
struct acpi_iort_id_mapping {
@@ -152,10 +153,17 @@ struct acpi_iort_named_component {
char device_name[1]; /* Path of namespace object */
};
/* Masks for Flags field above */
#define ACPI_IORT_NC_STALL_SUPPORTED (1)
#define ACPI_IORT_NC_PASID_BITS (31<<1)
struct acpi_iort_root_complex {
u64 memory_properties; /* Memory access properties */
u32 ats_attribute;
u32 pci_segment_number;
u8 memory_address_limit; /* Memory address size limit */
u8 reserved[3]; /* Reserved, must be zero */
};
/* Values for ats_attribute field above */
@@ -209,9 +217,7 @@ struct acpi_iort_smmu_v3 {
u32 pri_gsiv;
u32 gerr_gsiv;
u32 sync_gsiv;
u8 pxm;
u8 reserved1;
u16 reserved2;
u32 pxm;
u32 id_mapping_index;
};
@@ -224,9 +230,16 @@ struct acpi_iort_smmu_v3 {
/* Masks for Flags field above */
#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (1<<1)
#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1)
#define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3)
struct acpi_iort_pmcg {
u64 page0_base_address;
u32 overflow_gsiv;
u32 node_reference;
u64 page1_base_address;
};
/*******************************************************************************
*
* IVRS - I/O Virtualization Reporting Structure

5
include/acpi/actypes.h
View File

@@ -245,6 +245,10 @@ typedef u64 acpi_physical_address;
#define acpi_spinlock void *
#endif
#ifndef acpi_raw_spinlock
#define acpi_raw_spinlock acpi_spinlock
#endif
#ifndef acpi_semaphore
#define acpi_semaphore void *
#endif
@@ -1268,6 +1272,7 @@ typedef enum {
#define ACPI_OSI_WIN_10 0x0D
#define ACPI_OSI_WIN_10_RS1 0x0E
#define ACPI_OSI_WIN_10_RS2 0x0F
#define ACPI_OSI_WIN_10_RS3 0x10
/* Definitions of getopt */

14
include/acpi/cppc_acpi.h
View File

@@ -20,14 +20,16 @@
#include <acpi/pcc.h>
#include <acpi/processor.h>
/* Only support CPPCv2 for now. */
#define CPPC_NUM_ENT 21
#define CPPC_REV 2
/* Support CPPCv2 and CPPCv3 */
#define CPPC_V2_REV 2
#define CPPC_V3_REV 3
#define CPPC_V2_NUM_ENT 21
#define CPPC_V3_NUM_ENT 23
#define PCC_CMD_COMPLETE_MASK (1 << 0)
#define PCC_ERROR_MASK (1 << 2)
#define MAX_CPC_REG_ENT 19
#define MAX_CPC_REG_ENT 21
/* CPPC specific PCC commands. */
#define CMD_READ 0
@@ -91,6 +93,8 @@ enum cppc_regs {
AUTO_ACT_WINDOW,
ENERGY_PERF,
REFERENCE_PERF,
LOWEST_FREQ,
NOMINAL_FREQ,
};
/*
@@ -104,6 +108,8 @@ struct cppc_perf_caps {
u32 nominal_perf;
u32 lowest_perf;
u32 lowest_nonlinear_perf;
u32 lowest_freq;
u32 nominal_freq;
};
struct cppc_perf_ctrls {

7
include/acpi/ghes.h
View File

@@ -55,22 +55,21 @@ enum {
/* From drivers/edac/ghes_edac.c */
#ifdef CONFIG_EDAC_GHES
void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
struct cper_sec_mem_err *mem_err);
void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err);
int ghes_edac_register(struct ghes *ghes, struct device *dev);
void ghes_edac_unregister(struct ghes *ghes);
#else
static inline void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
static inline void ghes_edac_report_mem_error(int sev,
struct cper_sec_mem_err *mem_err)
{
}
static inline int ghes_edac_register(struct ghes *ghes, struct device *dev)
{
return 0;
return -ENODEV;
}
static inline void ghes_edac_unregister(struct ghes *ghes)

5
include/acpi/platform/aclinux.h
View File

@@ -102,6 +102,7 @@
#define acpi_cache_t struct kmem_cache
#define acpi_spinlock spinlock_t *
#define acpi_raw_spinlock raw_spinlock_t *
#define acpi_cpu_flags unsigned long
/* Use native linux version of acpi_os_allocate_zeroed */
@@ -119,6 +120,10 @@
#define ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_acquire_object
#define ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_get_thread_id
#define ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_create_lock
#define ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_create_raw_lock
#define ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_delete_raw_lock
#define ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_acquire_raw_lock
#define ACPI_USE_ALTERNATE_PROTOTYPE_acpi_os_release_raw_lock
/*
* OSL interfaces used by debugger/disassembler

30
include/acpi/platform/aclinuxex.h
View File

@@ -90,6 +90,36 @@ static inline acpi_thread_id acpi_os_get_thread_id(void)
lock ? AE_OK : AE_NO_MEMORY; \
})
#define acpi_os_create_raw_lock(__handle) \
({ \
raw_spinlock_t *lock = ACPI_ALLOCATE(sizeof(*lock)); \
if (lock) { \
*(__handle) = lock; \
raw_spin_lock_init(*(__handle)); \
} \
lock ? AE_OK : AE_NO_MEMORY; \
})
static inline acpi_cpu_flags acpi_os_acquire_raw_lock(acpi_raw_spinlock lockp)
{
acpi_cpu_flags flags;
raw_spin_lock_irqsave(lockp, flags);
return flags;
}
static inline void acpi_os_release_raw_lock(acpi_raw_spinlock lockp,
acpi_cpu_flags flags)
{
raw_spin_unlock_irqrestore(lockp, flags);
}
static inline void acpi_os_delete_raw_lock(acpi_raw_spinlock handle)
{
ACPI_FREE(handle);
}
static inline u8 acpi_os_readable(void *pointer, acpi_size length)
{
return TRUE;

3
include/acpi/processor.h
View File

@@ -309,7 +309,7 @@ static inline void acpi_processor_ppc_exit(void)
{
return;
}
static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr,
static inline void acpi_processor_ppc_has_changed(struct acpi_processor *pr,
int event_flag)
{
static unsigned int printout = 1;
@@ -320,7 +320,6 @@ static inline int acpi_processor_ppc_has_changed(struct acpi_processor *pr,
"Consider compiling CPUfreq support into your kernel.\n");
printout = 0;
}
return 0;
}
static inline int acpi_processor_get_bios_limit(int cpu, unsigned int *limit)
{

19
include/asm-generic/atomic-long.h
View File

@@ -25,6 +25,7 @@ typedef atomic64_t atomic_long_t;
#define ATOMIC_LONG_INIT(i) ATOMIC64_INIT(i)
#define ATOMIC_LONG_PFX(x) atomic64 ## x
#define ATOMIC_LONG_TYPE s64
#else
@@ -32,6 +33,7 @@ typedef atomic_t atomic_long_t;
#define ATOMIC_LONG_INIT(i) ATOMIC_INIT(i)
#define ATOMIC_LONG_PFX(x) atomic ## x
#define ATOMIC_LONG_TYPE int
#endif
@@ -90,6 +92,21 @@ ATOMIC_LONG_ADD_SUB_OP(sub, _release)
#define atomic_long_cmpxchg(l, old, new) \
(ATOMIC_LONG_PFX(_cmpxchg)((ATOMIC_LONG_PFX(_t) *)(l), (old), (new)))
#define atomic_long_try_cmpxchg_relaxed(l, old, new) \
(ATOMIC_LONG_PFX(_try_cmpxchg_relaxed)((ATOMIC_LONG_PFX(_t) *)(l), \
(ATOMIC_LONG_TYPE *)(old), (ATOMIC_LONG_TYPE)(new)))
#define atomic_long_try_cmpxchg_acquire(l, old, new) \
(ATOMIC_LONG_PFX(_try_cmpxchg_acquire)((ATOMIC_LONG_PFX(_t) *)(l), \
(ATOMIC_LONG_TYPE *)(old), (ATOMIC_LONG_TYPE)(new)))
#define atomic_long_try_cmpxchg_release(l, old, new) \
(ATOMIC_LONG_PFX(_try_cmpxchg_release)((ATOMIC_LONG_PFX(_t) *)(l), \
(ATOMIC_LONG_TYPE *)(old), (ATOMIC_LONG_TYPE)(new)))
#define atomic_long_try_cmpxchg(l, old, new) \
(ATOMIC_LONG_PFX(_try_cmpxchg)((ATOMIC_LONG_PFX(_t) *)(l), \
(ATOMIC_LONG_TYPE *)(old), (ATOMIC_LONG_TYPE)(new)))
#define atomic_long_xchg_relaxed(v, new) \
(ATOMIC_LONG_PFX(_xchg_relaxed)((ATOMIC_LONG_PFX(_t) *)(v), (new)))
#define atomic_long_xchg_acquire(v, new) \
@@ -244,6 +261,8 @@ static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
#define atomic_long_inc_not_zero(l) \
ATOMIC_LONG_PFX(_inc_not_zero)((ATOMIC_LONG_PFX(_t) *)(l))
#define atomic_long_cond_read_relaxed(v, c) \
ATOMIC_LONG_PFX(_cond_read_relaxed)((ATOMIC_LONG_PFX(_t) *)(v), (c))
#define atomic_long_cond_read_acquire(v, c) \
ATOMIC_LONG_PFX(_cond_read_acquire)((ATOMIC_LONG_PFX(_t) *)(v), (c))

27
include/asm-generic/barrier.h
View File

@@ -221,18 +221,17 @@ do { \
#endif
/**
* smp_cond_load_acquire() - (Spin) wait for cond with ACQUIRE ordering
* smp_cond_load_relaxed() - (Spin) wait for cond with no ordering guarantees
* @ptr: pointer to the variable to wait on
* @cond: boolean expression to wait for
*
* Equivalent to using smp_load_acquire() on the condition variable but employs
* the control dependency of the wait to reduce the barrier on many platforms.
* Equivalent to using READ_ONCE() on the condition variable.
*
* Due to C lacking lambda expressions we load the value of *ptr into a
* pre-named variable @VAL to be used in @cond.
*/
#ifndef smp_cond_load_acquire
#define smp_cond_load_acquire(ptr, cond_expr) ({ \
#ifndef smp_cond_load_relaxed
#define smp_cond_load_relaxed(ptr, cond_expr) ({ \
typeof(ptr) __PTR = (ptr); \
typeof(*ptr) VAL; \
for (;;) { \
@@ -241,10 +240,26 @@ do { \
break; \
cpu_relax(); \
} \
smp_acquire__after_ctrl_dep(); \
VAL; \
})
#endif
/**
* smp_cond_load_acquire() - (Spin) wait for cond with ACQUIRE ordering
* @ptr: pointer to the variable to wait on
* @cond: boolean expression to wait for
*
* Equivalent to using smp_load_acquire() on the condition variable but employs
* the control dependency of the wait to reduce the barrier on many platforms.
*/
#ifndef smp_cond_load_acquire
#define smp_cond_load_acquire(ptr, cond_expr) ({ \
typeof(*ptr) _val; \
_val = smp_cond_load_relaxed(ptr, cond_expr); \
smp_acquire__after_ctrl_dep(); \
_val; \
})
#endif
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_GENERIC_BARRIER_H */

3
include/asm-generic/compat.h Normal file
View File

@@ -0,0 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* This is an empty stub for 32-bit-only architectures */

9
include/asm-generic/dma-mapping.h
View File

@@ -4,7 +4,16 @@
static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
{
/*
* Use the non-coherent ops if available. If an architecture wants a
* more fine-grained selection of operations it will have to implement
* get_arch_dma_ops itself or use the per-device dma_ops.
*/
#ifdef CONFIG_DMA_NONCOHERENT_OPS
return &dma_noncoherent_ops;
#else
return &dma_direct_ops;
#endif
}
#endif /* _ASM_GENERIC_DMA_MAPPING_H */

34
include/asm-generic/export.h
View File

@@ -19,42 +19,32 @@
#define KCRC_ALIGN 4
#endif
#ifdef CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX
#define KSYM(name) _##name
#else
#define KSYM(name) name
#endif
/*
* note on .section use: @progbits vs %progbits nastiness doesn't matter,
* since we immediately emit into those sections anyway.
*/
.macro ___EXPORT_SYMBOL name,val,sec
#ifdef CONFIG_MODULES
.globl KSYM(__ksymtab_\name)
.globl __ksymtab_\name
.section ___ksymtab\sec+\name,"a"
.balign KSYM_ALIGN
KSYM(__ksymtab_\name):
__put \val, KSYM(__kstrtab_\name)
__ksymtab_\name:
__put \val, __kstrtab_\name
.previous
.section __ksymtab_strings,"a"
KSYM(__kstrtab_\name):
#ifdef CONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX
.asciz "_\name"
#else
__kstrtab_\name:
.asciz "\name"
#endif
.previous
#ifdef CONFIG_MODVERSIONS
.section ___kcrctab\sec+\name,"a"
.balign KCRC_ALIGN
KSYM(__kcrctab_\name):
__kcrctab_\name:
#if defined(CONFIG_MODULE_REL_CRCS)
.long KSYM(__crc_\name) - .
.long __crc_\name - .
#else
.long KSYM(__crc_\name)
.long __crc_\name
#endif
.weak KSYM(__crc_\name)
.weak __crc_\name
.previous
#endif
#endif
@@ -84,12 +74,12 @@ KSYM(__kcrctab_\name):
#endif
#define EXPORT_SYMBOL(name) \
__EXPORT_SYMBOL(name, KSYM_FUNC(KSYM(name)),)
__EXPORT_SYMBOL(name, KSYM_FUNC(name),)
#define EXPORT_SYMBOL_GPL(name) \
__EXPORT_SYMBOL(name, KSYM_FUNC(KSYM(name)), _gpl)
__EXPORT_SYMBOL(name, KSYM_FUNC(name), _gpl)
#define EXPORT_DATA_SYMBOL(name) \
__EXPORT_SYMBOL(name, KSYM(name),)
__EXPORT_SYMBOL(name, name,)
#define EXPORT_DATA_SYMBOL_GPL(name) \
__EXPORT_SYMBOL(name, KSYM(name),_gpl)
__EXPORT_SYMBOL(name, name,_gpl)
#endif

19
include/asm-generic/int-ll64.h
View File

@@ -13,17 +13,14 @@
#ifndef __ASSEMBLY__
typedef signed char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed int s32;
typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
typedef __s8 s8;
typedef __u8 u8;
typedef __s16 s16;
typedef __u16 u16;
typedef __s32 s32;
typedef __u32 u32;
typedef __s64 s64;
typedef __u64 u64;
#define S8_C(x) x
#define U8_C(x) x ## U

8
include/asm-generic/pci.h
View File

@@ -14,12 +14,4 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
}
#endif /* HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ */
/*
* By default, assume that no iommu is in use and that the PCI
* space is mapped to address physical 0.
*/
#ifndef PCI_DMA_BUS_IS_PHYS
#define PCI_DMA_BUS_IS_PHYS (1)
#endif
#endif /* _ASM_GENERIC_PCI_H */

4
include/asm-generic/qspinlock.h
View File

@@ -26,7 +26,6 @@
* @lock: Pointer to queued spinlock structure
* Return: 1 if it is locked, 0 otherwise
*/
#ifndef queued_spin_is_locked
static __always_inline int queued_spin_is_locked(struct qspinlock *lock)
{
/*
@@ -35,7 +34,6 @@ static __always_inline int queued_spin_is_locked(struct qspinlock *lock)
*/
return atomic_read(&lock->val);
}
#endif
/**
* queued_spin_value_unlocked - is the spinlock structure unlocked?
@@ -100,7 +98,7 @@ static __always_inline void queued_spin_unlock(struct qspinlock *lock)
/*
* unlock() needs release semantics:
*/
(void)atomic_sub_return_release(_Q_LOCKED_VAL, &lock->val);
smp_store_release(&lock->locked, 0);
}
#endif

32
include/asm-generic/qspinlock_types.h
View File

@@ -29,13 +29,41 @@
#endif
typedef struct qspinlock {
atomic_t val;
union {
atomic_t val;
/*
* By using the whole 2nd least significant byte for the
* pending bit, we can allow better optimization of the lock
* acquisition for the pending bit holder.
*/
#ifdef __LITTLE_ENDIAN
struct {
u8 locked;
u8 pending;
};
struct {
u16 locked_pending;
u16 tail;
};
#else
struct {
u16 tail;
u16 locked_pending;
};
struct {
u8 reserved[2];
u8 pending;
u8 locked;
};
#endif
};
} arch_spinlock_t;
/*
* Initializier
*/
#define __ARCH_SPIN_LOCK_UNLOCKED { ATOMIC_INIT(0) }
#define __ARCH_SPIN_LOCK_UNLOCKED { { .val = ATOMIC_INIT(0) } }
/*
* Bitfields in the atomic value:

334
include/asm-generic/vmlinux.lds.h
View File

@@ -64,15 +64,24 @@
* generates .data.identifier sections, which need to be pulled in with
* .data. We don't want to pull in .data..other sections, which Linux
* has defined. Same for text and bss.
*
* RODATA_MAIN is not used because existing code already defines .rodata.x
* sections to be brought in with rodata.
*/
#ifdef CONFIG_LD_DEAD_CODE_DATA_ELIMINATION
#define TEXT_MAIN .text .text.[0-9a-zA-Z_]*
#define DATA_MAIN .data .data.[0-9a-zA-Z_]*
#define SDATA_MAIN .sdata .sdata.[0-9a-zA-Z_]*
#define RODATA_MAIN .rodata .rodata.[0-9a-zA-Z_]*
#define BSS_MAIN .bss .bss.[0-9a-zA-Z_]*
#define SBSS_MAIN .sbss .sbss.[0-9a-zA-Z_]*
#else
#define TEXT_MAIN .text
#define DATA_MAIN .data
#define SDATA_MAIN .sdata
#define RODATA_MAIN .rodata
#define BSS_MAIN .bss
#define SBSS_MAIN .sbss
#endif
/*
@@ -104,66 +113,66 @@
#ifdef CONFIG_FTRACE_MCOUNT_RECORD
#define MCOUNT_REC() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_mcount_loc) = .; \
*(__mcount_loc) \
VMLINUX_SYMBOL(__stop_mcount_loc) = .;
__start_mcount_loc = .; \
KEEP(*(__mcount_loc)) \
__stop_mcount_loc = .;
#else
#define MCOUNT_REC()
#endif
#ifdef CONFIG_TRACE_BRANCH_PROFILING
#define LIKELY_PROFILE() VMLINUX_SYMBOL(__start_annotated_branch_profile) = .; \
*(_ftrace_annotated_branch) \
VMLINUX_SYMBOL(__stop_annotated_branch_profile) = .;
#define LIKELY_PROFILE() __start_annotated_branch_profile = .; \
KEEP(*(_ftrace_annotated_branch)) \
__stop_annotated_branch_profile = .;
#else
#define LIKELY_PROFILE()
#endif
#ifdef CONFIG_PROFILE_ALL_BRANCHES
#define BRANCH_PROFILE() VMLINUX_SYMBOL(__start_branch_profile) = .; \
*(_ftrace_branch) \
VMLINUX_SYMBOL(__stop_branch_profile) = .;
#define BRANCH_PROFILE() __start_branch_profile = .; \
KEEP(*(_ftrace_branch)) \
__stop_branch_profile = .;
#else
#define BRANCH_PROFILE()
#endif
#ifdef CONFIG_KPROBES
#define KPROBE_BLACKLIST() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_kprobe_blacklist) = .; \
__start_kprobe_blacklist = .; \
KEEP(*(_kprobe_blacklist)) \
VMLINUX_SYMBOL(__stop_kprobe_blacklist) = .;
__stop_kprobe_blacklist = .;
#else
#define KPROBE_BLACKLIST()
#endif
#ifdef CONFIG_FUNCTION_ERROR_INJECTION
#define ERROR_INJECT_WHITELIST() STRUCT_ALIGN(); \
VMLINUX_SYMBOL(__start_error_injection_whitelist) = .;\
__start_error_injection_whitelist = .; \
KEEP(*(_error_injection_whitelist)) \
VMLINUX_SYMBOL(__stop_error_injection_whitelist) = .;
__stop_error_injection_whitelist = .;
#else
#define ERROR_INJECT_WHITELIST()
#endif
#ifdef CONFIG_EVENT_TRACING
#define FTRACE_EVENTS() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_ftrace_events) = .; \
__start_ftrace_events = .; \
KEEP(*(_ftrace_events)) \
VMLINUX_SYMBOL(__stop_ftrace_events) = .; \
VMLINUX_SYMBOL(__start_ftrace_eval_maps) = .; \
__stop_ftrace_events = .; \
__start_ftrace_eval_maps = .; \
KEEP(*(_ftrace_eval_map)) \
VMLINUX_SYMBOL(__stop_ftrace_eval_maps) = .;
__stop_ftrace_eval_maps = .;
#else
#define FTRACE_EVENTS()
#endif
#ifdef CONFIG_TRACING
#define TRACE_PRINTKS() VMLINUX_SYMBOL(__start___trace_bprintk_fmt) = .; \
#define TRACE_PRINTKS() __start___trace_bprintk_fmt = .; \
KEEP(*(__trace_printk_fmt)) /* Trace_printk fmt' pointer */ \
VMLINUX_SYMBOL(__stop___trace_bprintk_fmt) = .;
#define TRACEPOINT_STR() VMLINUX_SYMBOL(__start___tracepoint_str) = .; \
__stop___trace_bprintk_fmt = .;
#define TRACEPOINT_STR() __start___tracepoint_str = .; \
KEEP(*(__tracepoint_str)) /* Trace_printk fmt' pointer */ \
VMLINUX_SYMBOL(__stop___tracepoint_str) = .;
__stop___tracepoint_str = .;
#else
#define TRACE_PRINTKS()
#define TRACEPOINT_STR()
@@ -171,27 +180,27 @@
#ifdef CONFIG_FTRACE_SYSCALLS
#define TRACE_SYSCALLS() . = ALIGN(8); \
VMLINUX_SYMBOL(__start_syscalls_metadata) = .; \
__start_syscalls_metadata = .; \
KEEP(*(__syscalls_metadata)) \
VMLINUX_SYMBOL(__stop_syscalls_metadata) = .;
__stop_syscalls_metadata = .;
#else
#define TRACE_SYSCALLS()
#endif
#ifdef CONFIG_BPF_EVENTS
#define BPF_RAW_TP() STRUCT_ALIGN(); \
VMLINUX_SYMBOL(__start__bpf_raw_tp) = .; \
__start__bpf_raw_tp = .; \
KEEP(*(__bpf_raw_tp_map)) \
VMLINUX_SYMBOL(__stop__bpf_raw_tp) = .;
__stop__bpf_raw_tp = .;
#else
#define BPF_RAW_TP()
#endif
#ifdef CONFIG_SERIAL_EARLYCON
#define EARLYCON_TABLE() . = ALIGN(8); \
VMLINUX_SYMBOL(__earlycon_table) = .; \
__earlycon_table = .; \
KEEP(*(__earlycon_table)) \
VMLINUX_SYMBOL(__earlycon_table_end) = .;
__earlycon_table_end = .;
#else
#define EARLYCON_TABLE()
#endif
@@ -202,7 +211,7 @@
#define _OF_TABLE_0(name)
#define _OF_TABLE_1(name) \
. = ALIGN(8); \
VMLINUX_SYMBOL(__##name##_of_table) = .; \
__##name##_of_table = .; \
KEEP(*(__##name##_of_table)) \
KEEP(*(__##name##_of_table_end))
@@ -217,18 +226,18 @@
#ifdef CONFIG_ACPI
#define ACPI_PROBE_TABLE(name) \
. = ALIGN(8); \
VMLINUX_SYMBOL(__##name##_acpi_probe_table) = .; \
__##name##_acpi_probe_table = .; \
KEEP(*(__##name##_acpi_probe_table)) \
VMLINUX_SYMBOL(__##name##_acpi_probe_table_end) = .;
__##name##_acpi_probe_table_end = .;
#else
#define ACPI_PROBE_TABLE(name)
#endif
#define KERNEL_DTB() \
STRUCT_ALIGN(); \
VMLINUX_SYMBOL(__dtb_start) = .; \
__dtb_start = .; \
KEEP(*(.dtb.init.rodata)) \
VMLINUX_SYMBOL(__dtb_end) = .;
__dtb_end = .;
/*
* .data section
@@ -238,23 +247,23 @@
*(DATA_MAIN) \
*(.ref.data) \
*(.data..shared_aligned) /* percpu related */ \
MEM_KEEP(init.data) \
MEM_KEEP(exit.data) \
MEM_KEEP(init.data*) \
MEM_KEEP(exit.data*) \
*(.data.unlikely) \
VMLINUX_SYMBOL(__start_once) = .; \
__start_once = .; \
*(.data.once) \
VMLINUX_SYMBOL(__end_once) = .; \
__end_once = .; \
STRUCT_ALIGN(); \
*(__tracepoints) \
/* implement dynamic printk debug */ \
. = ALIGN(8); \
VMLINUX_SYMBOL(__start___jump_table) = .; \
__start___jump_table = .; \
KEEP(*(__jump_table)) \
VMLINUX_SYMBOL(__stop___jump_table) = .; \
__stop___jump_table = .; \
. = ALIGN(8); \
VMLINUX_SYMBOL(__start___verbose) = .; \
__start___verbose = .; \
KEEP(*(__verbose)) \
VMLINUX_SYMBOL(__stop___verbose) = .; \
__stop___verbose = .; \
LIKELY_PROFILE() \
BRANCH_PROFILE() \
TRACE_PRINTKS() \
@@ -266,10 +275,10 @@
*/
#define NOSAVE_DATA \
. = ALIGN(PAGE_SIZE); \
VMLINUX_SYMBOL(__nosave_begin) = .; \
__nosave_begin = .; \
*(.data..nosave) \
. = ALIGN(PAGE_SIZE); \
VMLINUX_SYMBOL(__nosave_end) = .;
__nosave_end = .;
#define PAGE_ALIGNED_DATA(page_align) \
. = ALIGN(page_align); \
@@ -286,13 +295,13 @@
#define INIT_TASK_DATA(align) \
. = ALIGN(align); \
VMLINUX_SYMBOL(__start_init_task) = .; \
VMLINUX_SYMBOL(init_thread_union) = .; \
VMLINUX_SYMBOL(init_stack) = .; \
*(.data..init_task) \
*(.data..init_thread_info) \
. = VMLINUX_SYMBOL(__start_init_task) + THREAD_SIZE; \
VMLINUX_SYMBOL(__end_init_task) = .;
__start_init_task = .; \
init_thread_union = .; \
init_stack = .; \
KEEP(*(.data..init_task)) \
KEEP(*(.data..init_thread_info)) \
. = __start_init_task + THREAD_SIZE; \
__end_init_task = .;
/*
* Allow architectures to handle ro_after_init data on their
@@ -300,9 +309,9 @@
*/
#ifndef RO_AFTER_INIT_DATA
#define RO_AFTER_INIT_DATA \
VMLINUX_SYMBOL(__start_ro_after_init) = .; \
__start_ro_after_init = .; \
*(.data..ro_after_init) \
VMLINUX_SYMBOL(__end_ro_after_init) = .;
__end_ro_after_init = .;
#endif
/*
@@ -311,14 +320,14 @@
#define RO_DATA_SECTION(align) \
. = ALIGN((align)); \
.rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start_rodata) = .; \
__start_rodata = .; \
*(.rodata) *(.rodata.*) \
RO_AFTER_INIT_DATA /* Read only after init */ \
KEEP(*(__vermagic)) /* Kernel version magic */ \
. = ALIGN(8); \
VMLINUX_SYMBOL(__start___tracepoints_ptrs) = .; \
__start___tracepoints_ptrs = .; \
KEEP(*(__tracepoints_ptrs)) /* Tracepoints: pointer array */ \
VMLINUX_SYMBOL(__stop___tracepoints_ptrs) = .; \
__stop___tracepoints_ptrs = .; \
*(__tracepoints_strings)/* Tracepoints: strings */ \
} \
\
@@ -328,109 +337,109 @@
\
/* PCI quirks */ \
.pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \
__start_pci_fixups_early = .; \
KEEP(*(.pci_fixup_early)) \
VMLINUX_SYMBOL(__end_pci_fixups_early) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_header) = .; \
__end_pci_fixups_early = .; \
__start_pci_fixups_header = .; \
KEEP(*(.pci_fixup_header)) \
VMLINUX_SYMBOL(__end_pci_fixups_header) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_final) = .; \
__end_pci_fixups_header = .; \
__start_pci_fixups_final = .; \
KEEP(*(.pci_fixup_final)) \
VMLINUX_SYMBOL(__end_pci_fixups_final) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_enable) = .; \
__end_pci_fixups_final = .; \
__start_pci_fixups_enable = .; \
KEEP(*(.pci_fixup_enable)) \
VMLINUX_SYMBOL(__end_pci_fixups_enable) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_resume) = .; \
__end_pci_fixups_enable = .; \
__start_pci_fixups_resume = .; \
KEEP(*(.pci_fixup_resume)) \
VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .; \
__end_pci_fixups_resume = .; \
__start_pci_fixups_resume_early = .; \
KEEP(*(.pci_fixup_resume_early)) \
VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \
__end_pci_fixups_resume_early = .; \
__start_pci_fixups_suspend = .; \
KEEP(*(.pci_fixup_suspend)) \
VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \
VMLINUX_SYMBOL(__start_pci_fixups_suspend_late) = .; \
__end_pci_fixups_suspend = .; \
__start_pci_fixups_suspend_late = .; \
KEEP(*(.pci_fixup_suspend_late)) \
VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \
__end_pci_fixups_suspend_late = .; \
} \
\
/* Built-in firmware blobs */ \
.builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start_builtin_fw) = .; \
__start_builtin_fw = .; \
KEEP(*(.builtin_fw)) \
VMLINUX_SYMBOL(__end_builtin_fw) = .; \
__end_builtin_fw = .; \
} \
\
TRACEDATA \
\
/* Kernel symbol table: Normal symbols */ \
__ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___ksymtab) = .; \
__start___ksymtab = .; \
KEEP(*(SORT(___ksymtab+*))) \
VMLINUX_SYMBOL(__stop___ksymtab) = .; \
__stop___ksymtab = .; \
} \
\
/* Kernel symbol table: GPL-only symbols */ \
__ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \
__start___ksymtab_gpl = .; \
KEEP(*(SORT(___ksymtab_gpl+*))) \
VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \
__stop___ksymtab_gpl = .; \
} \
\
/* Kernel symbol table: Normal unused symbols */ \
__ksymtab_unused : AT(ADDR(__ksymtab_unused) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___ksymtab_unused) = .; \
__start___ksymtab_unused = .; \
KEEP(*(SORT(___ksymtab_unused+*))) \
VMLINUX_SYMBOL(__stop___ksymtab_unused) = .; \
__stop___ksymtab_unused = .; \
} \
\
/* Kernel symbol table: GPL-only unused symbols */ \
__ksymtab_unused_gpl : AT(ADDR(__ksymtab_unused_gpl) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___ksymtab_unused_gpl) = .; \
__start___ksymtab_unused_gpl = .; \
KEEP(*(SORT(___ksymtab_unused_gpl+*))) \
VMLINUX_SYMBOL(__stop___ksymtab_unused_gpl) = .; \
__stop___ksymtab_unused_gpl = .; \
} \
\
/* Kernel symbol table: GPL-future-only symbols */ \
__ksymtab_gpl_future : AT(ADDR(__ksymtab_gpl_future) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___ksymtab_gpl_future) = .; \
__start___ksymtab_gpl_future = .; \
KEEP(*(SORT(___ksymtab_gpl_future+*))) \
VMLINUX_SYMBOL(__stop___ksymtab_gpl_future) = .; \
__stop___ksymtab_gpl_future = .; \
} \
\
/* Kernel symbol table: Normal symbols */ \
__kcrctab : AT(ADDR(__kcrctab) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___kcrctab) = .; \
__start___kcrctab = .; \
KEEP(*(SORT(___kcrctab+*))) \
VMLINUX_SYMBOL(__stop___kcrctab) = .; \
__stop___kcrctab = .; \
} \
\
/* Kernel symbol table: GPL-only symbols */ \
__kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___kcrctab_gpl) = .; \
__start___kcrctab_gpl = .; \
KEEP(*(SORT(___kcrctab_gpl+*))) \
VMLINUX_SYMBOL(__stop___kcrctab_gpl) = .; \
__stop___kcrctab_gpl = .; \
} \
\
/* Kernel symbol table: Normal unused symbols */ \
__kcrctab_unused : AT(ADDR(__kcrctab_unused) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___kcrctab_unused) = .; \
__start___kcrctab_unused = .; \
KEEP(*(SORT(___kcrctab_unused+*))) \
VMLINUX_SYMBOL(__stop___kcrctab_unused) = .; \
__stop___kcrctab_unused = .; \
} \
\
/* Kernel symbol table: GPL-only unused symbols */ \
__kcrctab_unused_gpl : AT(ADDR(__kcrctab_unused_gpl) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___kcrctab_unused_gpl) = .; \
__start___kcrctab_unused_gpl = .; \
KEEP(*(SORT(___kcrctab_unused_gpl+*))) \
VMLINUX_SYMBOL(__stop___kcrctab_unused_gpl) = .; \
__stop___kcrctab_unused_gpl = .; \
} \
\
/* Kernel symbol table: GPL-future-only symbols */ \
__kcrctab_gpl_future : AT(ADDR(__kcrctab_gpl_future) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___kcrctab_gpl_future) = .; \
__start___kcrctab_gpl_future = .; \
KEEP(*(SORT(___kcrctab_gpl_future+*))) \
VMLINUX_SYMBOL(__stop___kcrctab_gpl_future) = .; \
__stop___kcrctab_gpl_future = .; \
} \
\
/* Kernel symbol table: strings */ \
@@ -447,18 +456,18 @@
\
/* Built-in module parameters. */ \
__param : AT(ADDR(__param) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___param) = .; \
__start___param = .; \
KEEP(*(__param)) \
VMLINUX_SYMBOL(__stop___param) = .; \
__stop___param = .; \
} \
\
/* Built-in module versions. */ \
__modver : AT(ADDR(__modver) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___modver) = .; \
__start___modver = .; \
KEEP(*(__modver)) \
VMLINUX_SYMBOL(__stop___modver) = .; \
__stop___modver = .; \
. = ALIGN((align)); \
VMLINUX_SYMBOL(__end_rodata) = .; \
__end_rodata = .; \
} \
. = ALIGN((align));
@@ -469,9 +478,9 @@
#define SECURITY_INIT \
.security_initcall.init : AT(ADDR(.security_initcall.init) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__security_initcall_start) = .; \
__security_initcall_start = .; \
KEEP(*(.security_initcall.init)) \
VMLINUX_SYMBOL(__security_initcall_end) = .; \
__security_initcall_end = .; \
}
/*
@@ -487,58 +496,58 @@
*(.text.hot TEXT_MAIN .text.fixup .text.unlikely) \
*(.text..refcount) \
*(.ref.text) \
MEM_KEEP(init.text) \
MEM_KEEP(exit.text) \
MEM_KEEP(init.text*) \
MEM_KEEP(exit.text*) \
/* sched.text is aling to function alignment to secure we have same
* address even at second ld pass when generating System.map */
#define SCHED_TEXT \
ALIGN_FUNCTION(); \
VMLINUX_SYMBOL(__sched_text_start) = .; \
__sched_text_start = .; \
*(.sched.text) \
VMLINUX_SYMBOL(__sched_text_end) = .;
__sched_text_end = .;
/* spinlock.text is aling to function alignment to secure we have same
* address even at second ld pass when generating System.map */
#define LOCK_TEXT \
ALIGN_FUNCTION(); \
VMLINUX_SYMBOL(__lock_text_start) = .; \
__lock_text_start = .; \
*(.spinlock.text) \
VMLINUX_SYMBOL(__lock_text_end) = .;
__lock_text_end = .;
#define CPUIDLE_TEXT \
ALIGN_FUNCTION(); \
VMLINUX_SYMBOL(__cpuidle_text_start) = .; \
__cpuidle_text_start = .; \
*(.cpuidle.text) \
VMLINUX_SYMBOL(__cpuidle_text_end) = .;
__cpuidle_text_end = .;
#define KPROBES_TEXT \
ALIGN_FUNCTION(); \
VMLINUX_SYMBOL(__kprobes_text_start) = .; \
__kprobes_text_start = .; \
*(.kprobes.text) \
VMLINUX_SYMBOL(__kprobes_text_end) = .;
__kprobes_text_end = .;
#define ENTRY_TEXT \
ALIGN_FUNCTION(); \
VMLINUX_SYMBOL(__entry_text_start) = .; \
__entry_text_start = .; \
*(.entry.text) \
VMLINUX_SYMBOL(__entry_text_end) = .;
__entry_text_end = .;
#define IRQENTRY_TEXT \
ALIGN_FUNCTION(); \
VMLINUX_SYMBOL(__irqentry_text_start) = .; \
__irqentry_text_start = .; \
*(.irqentry.text) \
VMLINUX_SYMBOL(__irqentry_text_end) = .;
__irqentry_text_end = .;
#define SOFTIRQENTRY_TEXT \
ALIGN_FUNCTION(); \
VMLINUX_SYMBOL(__softirqentry_text_start) = .; \
__softirqentry_text_start = .; \
*(.softirqentry.text) \
VMLINUX_SYMBOL(__softirqentry_text_end) = .;
__softirqentry_text_end = .;
/* Section used for early init (in .S files) */
#define HEAD_TEXT *(.head.text)
#define HEAD_TEXT KEEP(*(.head.text))
#define HEAD_TEXT_SECTION \
.head.text : AT(ADDR(.head.text) - LOAD_OFFSET) { \
@@ -551,9 +560,9 @@
#define EXCEPTION_TABLE(align) \
. = ALIGN(align); \
__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___ex_table) = .; \
__start___ex_table = .; \
KEEP(*(__ex_table)) \
VMLINUX_SYMBOL(__stop___ex_table) = .; \
__stop___ex_table = .; \
}
/*
@@ -567,11 +576,11 @@
#ifdef CONFIG_CONSTRUCTORS
#define KERNEL_CTORS() . = ALIGN(8); \
VMLINUX_SYMBOL(__ctors_start) = .; \
__ctors_start = .; \
KEEP(*(.ctors)) \
KEEP(*(SORT(.init_array.*))) \
KEEP(*(.init_array)) \
VMLINUX_SYMBOL(__ctors_end) = .;
__ctors_end = .;
#else
#define KERNEL_CTORS()
#endif
@@ -579,11 +588,11 @@
/* init and exit section handling */
#define INIT_DATA \
KEEP(*(SORT(___kentry+*))) \
*(.init.data) \
MEM_DISCARD(init.data) \
*(.init.data init.data.*) \
MEM_DISCARD(init.data*) \
KERNEL_CTORS() \
MCOUNT_REC() \
*(.init.rodata) \
*(.init.rodata .init.rodata.*) \
FTRACE_EVENTS() \
TRACE_SYSCALLS() \
KPROBE_BLACKLIST() \
@@ -602,16 +611,16 @@
EARLYCON_TABLE()
#define INIT_TEXT \
*(.init.text) \
*(.init.text .init.text.*) \
*(.text.startup) \
MEM_DISCARD(init.text)
MEM_DISCARD(init.text*)
#define EXIT_DATA \
*(.exit.data) \
*(.exit.data .exit.data.*) \
*(.fini_array) \
*(.dtors) \
MEM_DISCARD(exit.data) \
MEM_DISCARD(exit.rodata)
MEM_DISCARD(exit.data*) \
MEM_DISCARD(exit.rodata*)
#define EXIT_TEXT \
*(.exit.text) \
@@ -629,7 +638,7 @@
. = ALIGN(sbss_align); \
.sbss : AT(ADDR(.sbss) - LOAD_OFFSET) { \
*(.dynsbss) \
*(.sbss) \
*(SBSS_MAIN) \
*(.scommon) \
}
@@ -706,9 +715,9 @@
#define BUG_TABLE \
. = ALIGN(8); \
__bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start___bug_table) = .; \
__start___bug_table = .; \
KEEP(*(__bug_table)) \
VMLINUX_SYMBOL(__stop___bug_table) = .; \
__stop___bug_table = .; \
}
#else
#define BUG_TABLE
@@ -718,22 +727,22 @@
#define ORC_UNWIND_TABLE \
. = ALIGN(4); \
.orc_unwind_ip : AT(ADDR(.orc_unwind_ip) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start_orc_unwind_ip) = .; \
__start_orc_unwind_ip = .; \
KEEP(*(.orc_unwind_ip)) \
VMLINUX_SYMBOL(__stop_orc_unwind_ip) = .; \
__stop_orc_unwind_ip = .; \
} \
. = ALIGN(6); \
.orc_unwind : AT(ADDR(.orc_unwind) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start_orc_unwind) = .; \
__start_orc_unwind = .; \
KEEP(*(.orc_unwind)) \
VMLINUX_SYMBOL(__stop_orc_unwind) = .; \
__stop_orc_unwind = .; \
} \
. = ALIGN(4); \
.orc_lookup : AT(ADDR(.orc_lookup) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(orc_lookup) = .; \
orc_lookup = .; \
. += (((SIZEOF(.text) + LOOKUP_BLOCK_SIZE - 1) / \
LOOKUP_BLOCK_SIZE) + 1) * 4; \
VMLINUX_SYMBOL(orc_lookup_end) = .; \
orc_lookup_end = .; \
}
#else
#define ORC_UNWIND_TABLE
@@ -743,9 +752,9 @@
#define TRACEDATA \
. = ALIGN(4); \
.tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__tracedata_start) = .; \
__tracedata_start = .; \
KEEP(*(.tracedata)) \
VMLINUX_SYMBOL(__tracedata_end) = .; \
__tracedata_end = .; \
}
#else
#define TRACEDATA
@@ -753,24 +762,24 @@
#define NOTES \
.notes : AT(ADDR(.notes) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__start_notes) = .; \
*(.note.*) \
VMLINUX_SYMBOL(__stop_notes) = .; \
__start_notes = .; \
KEEP(*(.note.*)) \
__stop_notes = .; \
}
#define INIT_SETUP(initsetup_align) \
. = ALIGN(initsetup_align); \
VMLINUX_SYMBOL(__setup_start) = .; \
__setup_start = .; \
KEEP(*(.init.setup)) \
VMLINUX_SYMBOL(__setup_end) = .;
__setup_end = .;
#define INIT_CALLS_LEVEL(level) \
VMLINUX_SYMBOL(__initcall##level##_start) = .; \
__initcall##level##_start = .; \
KEEP(*(.initcall##level##.init)) \
KEEP(*(.initcall##level##s.init)) \
#define INIT_CALLS \
VMLINUX_SYMBOL(__initcall_start) = .; \
__initcall_start = .; \
KEEP(*(.initcallearly.init)) \
INIT_CALLS_LEVEL(0) \
INIT_CALLS_LEVEL(1) \
@@ -781,22 +790,22 @@
INIT_CALLS_LEVEL(rootfs) \
INIT_CALLS_LEVEL(6) \
INIT_CALLS_LEVEL(7) \
VMLINUX_SYMBOL(__initcall_end) = .;
__initcall_end = .;
#define CON_INITCALL \
VMLINUX_SYMBOL(__con_initcall_start) = .; \
__con_initcall_start = .; \
KEEP(*(.con_initcall.init)) \
VMLINUX_SYMBOL(__con_initcall_end) = .;
__con_initcall_end = .;
#define SECURITY_INITCALL \
VMLINUX_SYMBOL(__security_initcall_start) = .; \
__security_initcall_start = .; \
KEEP(*(.security_initcall.init)) \
VMLINUX_SYMBOL(__security_initcall_end) = .;
__security_initcall_end = .;
#ifdef CONFIG_BLK_DEV_INITRD
#define INIT_RAM_FS \
. = ALIGN(4); \
VMLINUX_SYMBOL(__initramfs_start) = .; \
__initramfs_start = .; \
KEEP(*(.init.ramfs)) \
. = ALIGN(8); \
KEEP(*(.init.ramfs.info))
@@ -851,7 +860,7 @@
* sharing between subsections for different purposes.
*/
#define PERCPU_INPUT(cacheline) \
VMLINUX_SYMBOL(__per_cpu_start) = .; \
__per_cpu_start = .; \
*(.data..percpu..first) \
. = ALIGN(PAGE_SIZE); \
*(.data..percpu..page_aligned) \
@@ -861,7 +870,7 @@
*(.data..percpu) \
*(.data..percpu..shared_aligned) \
PERCPU_DECRYPTED_SECTION \
VMLINUX_SYMBOL(__per_cpu_end) = .;
__per_cpu_end = .;
/**
* PERCPU_VADDR - define output section for percpu area
@@ -888,12 +897,11 @@
* address, use PERCPU_SECTION.
*/
#define PERCPU_VADDR(cacheline, vaddr, phdr) \
VMLINUX_SYMBOL(__per_cpu_load) = .; \
.data..percpu vaddr : AT(VMLINUX_SYMBOL(__per_cpu_load) \
- LOAD_OFFSET) { \
__per_cpu_load = .; \
.data..percpu vaddr : AT(__per_cpu_load - LOAD_OFFSET) { \
PERCPU_INPUT(cacheline) \
} phdr \
. = VMLINUX_SYMBOL(__per_cpu_load) + SIZEOF(.data..percpu);
. = __per_cpu_load + SIZEOF(.data..percpu);
/**
* PERCPU_SECTION - define output section for percpu area, simple version
@@ -910,7 +918,7 @@
#define PERCPU_SECTION(cacheline) \
. = ALIGN(PAGE_SIZE); \
.data..percpu : AT(ADDR(.data..percpu) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__per_cpu_load) = .; \
__per_cpu_load = .; \
PERCPU_INPUT(cacheline) \
}
@@ -949,9 +957,9 @@
#define INIT_TEXT_SECTION(inittext_align) \
. = ALIGN(inittext_align); \
.init.text : AT(ADDR(.init.text) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(_sinittext) = .; \
_sinittext = .; \
INIT_TEXT \
VMLINUX_SYMBOL(_einittext) = .; \
_einittext = .; \
}
#define INIT_DATA_SECTION(initsetup_align) \
@@ -966,8 +974,8 @@
#define BSS_SECTION(sbss_align, bss_align, stop_align) \
. = ALIGN(sbss_align); \
VMLINUX_SYMBOL(__bss_start) = .; \
__bss_start = .; \
SBSS(sbss_align) \
BSS(bss_align) \
. = ALIGN(stop_align); \
VMLINUX_SYMBOL(__bss_stop) = .;
__bss_stop = .;

8
include/crypto/algapi.h
View File

@@ -17,6 +17,14 @@
#include <linux/kernel.h>
#include <linux/skbuff.h>
/*
* Maximum values for blocksize and alignmask, used to allocate
* static buffers that are big enough for any combination of
* ciphers and architectures.
*/
#define MAX_CIPHER_BLOCKSIZE 16
#define MAX_CIPHER_ALIGNMASK 15
struct crypto_aead;
struct crypto_instance;
struct module;

137
include/crypto/morus1280_glue.h Normal file
View File

@@ -0,0 +1,137 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* The MORUS-1280 Authenticated-Encryption Algorithm
* Common glue skeleton -- header file
*
* Copyright (c) 2016-2018 Ondrej Mosnacek <omosnacek@gmail.com>
* Copyright (C) 2017-2018 Red Hat, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#ifndef _CRYPTO_MORUS1280_GLUE_H
#define _CRYPTO_MORUS1280_GLUE_H
#include <linux/module.h>
#include <linux/types.h>
#include <crypto/algapi.h>
#include <crypto/aead.h>
#include <crypto/morus_common.h>
#define MORUS1280_WORD_SIZE 8
#define MORUS1280_BLOCK_SIZE (MORUS_BLOCK_WORDS * MORUS1280_WORD_SIZE)
struct morus1280_block {
u8 bytes[MORUS1280_BLOCK_SIZE];
};
struct morus1280_glue_ops {
void (*init)(void *state, const void *key, const void *iv);
void (*ad)(void *state, const void *data, unsigned int length);
void (*enc)(void *state, const void *src, void *dst, unsigned int length);
void (*dec)(void *state, const void *src, void *dst, unsigned int length);
void (*enc_tail)(void *state, const void *src, void *dst, unsigned int length);
void (*dec_tail)(void *state, const void *src, void *dst, unsigned int length);
void (*final)(void *state, void *tag_xor, u64 assoclen, u64 cryptlen);
};
struct morus1280_ctx {
const struct morus1280_glue_ops *ops;
struct morus1280_block key;
};
void crypto_morus1280_glue_init_ops(struct crypto_aead *aead,
const struct morus1280_glue_ops *ops);
int crypto_morus1280_glue_setkey(struct crypto_aead *aead, const u8 *key,
unsigned int keylen);
int crypto_morus1280_glue_setauthsize(struct crypto_aead *tfm,
unsigned int authsize);
int crypto_morus1280_glue_encrypt(struct aead_request *req);
int crypto_morus1280_glue_decrypt(struct aead_request *req);
int cryptd_morus1280_glue_setkey(struct crypto_aead *aead, const u8 *key,
unsigned int keylen);
int cryptd_morus1280_glue_setauthsize(struct crypto_aead *aead,
unsigned int authsize);
int cryptd_morus1280_glue_encrypt(struct aead_request *req);
int cryptd_morus1280_glue_decrypt(struct aead_request *req);
int cryptd_morus1280_glue_init_tfm(struct crypto_aead *aead);
void cryptd_morus1280_glue_exit_tfm(struct crypto_aead *aead);
#define MORUS1280_DECLARE_ALGS(id, driver_name, priority) \
static const struct morus1280_glue_ops crypto_morus1280_##id##_ops = {\
.init = crypto_morus1280_##id##_init, \
.ad = crypto_morus1280_##id##_ad, \
.enc = crypto_morus1280_##id##_enc, \
.enc_tail = crypto_morus1280_##id##_enc_tail, \
.dec = crypto_morus1280_##id##_dec, \
.dec_tail = crypto_morus1280_##id##_dec_tail, \
.final = crypto_morus1280_##id##_final, \
}; \
\
static int crypto_morus1280_##id##_init_tfm(struct crypto_aead *tfm) \
{ \
crypto_morus1280_glue_init_ops(tfm, &crypto_morus1280_##id##_ops); \
return 0; \
} \
\
static void crypto_morus1280_##id##_exit_tfm(struct crypto_aead *tfm) \
{ \
} \
\
struct aead_alg crypto_morus1280_##id##_algs[] = {\
{ \
.setkey = crypto_morus1280_glue_setkey, \
.setauthsize = crypto_morus1280_glue_setauthsize, \
.encrypt = crypto_morus1280_glue_encrypt, \
.decrypt = crypto_morus1280_glue_decrypt, \
.init = crypto_morus1280_##id##_init_tfm, \
.exit = crypto_morus1280_##id##_exit_tfm, \
\
.ivsize = MORUS_NONCE_SIZE, \
.maxauthsize = MORUS_MAX_AUTH_SIZE, \
.chunksize = MORUS1280_BLOCK_SIZE, \
\
.base = { \
.cra_flags = CRYPTO_ALG_INTERNAL, \
.cra_blocksize = 1, \
.cra_ctxsize = sizeof(struct morus1280_ctx), \
.cra_alignmask = 0, \
\
.cra_name = "__morus1280", \
.cra_driver_name = "__"driver_name, \
\
.cra_module = THIS_MODULE, \
} \
}, { \
.setkey = cryptd_morus1280_glue_setkey, \
.setauthsize = cryptd_morus1280_glue_setauthsize, \
.encrypt = cryptd_morus1280_glue_encrypt, \
.decrypt = cryptd_morus1280_glue_decrypt, \
.init = cryptd_morus1280_glue_init_tfm, \
.exit = cryptd_morus1280_glue_exit_tfm, \
\
.ivsize = MORUS_NONCE_SIZE, \
.maxauthsize = MORUS_MAX_AUTH_SIZE, \
.chunksize = MORUS1280_BLOCK_SIZE, \
\
.base = { \
.cra_flags = CRYPTO_ALG_ASYNC, \
.cra_blocksize = 1, \
.cra_ctxsize = sizeof(struct crypto_aead *), \
.cra_alignmask = 0, \
\
.cra_priority = priority, \
\
.cra_name = "morus1280", \
.cra_driver_name = driver_name, \
\
.cra_module = THIS_MODULE, \
} \
} \
}
#endif /* _CRYPTO_MORUS1280_GLUE_H */

137
include/crypto/morus640_glue.h Normal file
View File

@@ -0,0 +1,137 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* The MORUS-640 Authenticated-Encryption Algorithm
* Common glue skeleton -- header file
*
* Copyright (c) 2016-2018 Ondrej Mosnacek <omosnacek@gmail.com>
* Copyright (C) 2017-2018 Red Hat, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#ifndef _CRYPTO_MORUS640_GLUE_H
#define _CRYPTO_MORUS640_GLUE_H
#include <linux/module.h>
#include <linux/types.h>
#include <crypto/algapi.h>
#include <crypto/aead.h>
#include <crypto/morus_common.h>
#define MORUS640_WORD_SIZE 4
#define MORUS640_BLOCK_SIZE (MORUS_BLOCK_WORDS * MORUS640_WORD_SIZE)
struct morus640_block {
u8 bytes[MORUS640_BLOCK_SIZE];
};
struct morus640_glue_ops {
void (*init)(void *state, const void *key, const void *iv);
void (*ad)(void *state, const void *data, unsigned int length);
void (*enc)(void *state, const void *src, void *dst, unsigned int length);
void (*dec)(void *state, const void *src, void *dst, unsigned int length);
void (*enc_tail)(void *state, const void *src, void *dst, unsigned int length);
void (*dec_tail)(void *state, const void *src, void *dst, unsigned int length);
void (*final)(void *state, void *tag_xor, u64 assoclen, u64 cryptlen);
};
struct morus640_ctx {
const struct morus640_glue_ops *ops;
struct morus640_block key;
};
void crypto_morus640_glue_init_ops(struct crypto_aead *aead,
const struct morus640_glue_ops *ops);
int crypto_morus640_glue_setkey(struct crypto_aead *aead, const u8 *key,
unsigned int keylen);
int crypto_morus640_glue_setauthsize(struct crypto_aead *tfm,
unsigned int authsize);
int crypto_morus640_glue_encrypt(struct aead_request *req);
int crypto_morus640_glue_decrypt(struct aead_request *req);
int cryptd_morus640_glue_setkey(struct crypto_aead *aead, const u8 *key,
unsigned int keylen);
int cryptd_morus640_glue_setauthsize(struct crypto_aead *aead,
unsigned int authsize);
int cryptd_morus640_glue_encrypt(struct aead_request *req);
int cryptd_morus640_glue_decrypt(struct aead_request *req);
int cryptd_morus640_glue_init_tfm(struct crypto_aead *aead);
void cryptd_morus640_glue_exit_tfm(struct crypto_aead *aead);
#define MORUS640_DECLARE_ALGS(id, driver_name, priority) \
static const struct morus640_glue_ops crypto_morus640_##id##_ops = {\
.init = crypto_morus640_##id##_init, \
.ad = crypto_morus640_##id##_ad, \
.enc = crypto_morus640_##id##_enc, \
.enc_tail = crypto_morus640_##id##_enc_tail, \
.dec = crypto_morus640_##id##_dec, \
.dec_tail = crypto_morus640_##id##_dec_tail, \
.final = crypto_morus640_##id##_final, \
}; \
\
static int crypto_morus640_##id##_init_tfm(struct crypto_aead *tfm) \
{ \
crypto_morus640_glue_init_ops(tfm, &crypto_morus640_##id##_ops); \
return 0; \
} \
\
static void crypto_morus640_##id##_exit_tfm(struct crypto_aead *tfm) \
{ \
} \
\
struct aead_alg crypto_morus640_##id##_algs[] = {\
{ \
.setkey = crypto_morus640_glue_setkey, \
.setauthsize = crypto_morus640_glue_setauthsize, \
.encrypt = crypto_morus640_glue_encrypt, \
.decrypt = crypto_morus640_glue_decrypt, \
.init = crypto_morus640_##id##_init_tfm, \
.exit = crypto_morus640_##id##_exit_tfm, \
\
.ivsize = MORUS_NONCE_SIZE, \
.maxauthsize = MORUS_MAX_AUTH_SIZE, \
.chunksize = MORUS640_BLOCK_SIZE, \
\
.base = { \
.cra_flags = CRYPTO_ALG_INTERNAL, \
.cra_blocksize = 1, \
.cra_ctxsize = sizeof(struct morus640_ctx), \
.cra_alignmask = 0, \
\
.cra_name = "__morus640", \
.cra_driver_name = "__"driver_name, \
\
.cra_module = THIS_MODULE, \
} \
}, { \
.setkey = cryptd_morus640_glue_setkey, \
.setauthsize = cryptd_morus640_glue_setauthsize, \
.encrypt = cryptd_morus640_glue_encrypt, \
.decrypt = cryptd_morus640_glue_decrypt, \
.init = cryptd_morus640_glue_init_tfm, \
.exit = cryptd_morus640_glue_exit_tfm, \
\
.ivsize = MORUS_NONCE_SIZE, \
.maxauthsize = MORUS_MAX_AUTH_SIZE, \
.chunksize = MORUS640_BLOCK_SIZE, \
\
.base = { \
.cra_flags = CRYPTO_ALG_ASYNC, \
.cra_blocksize = 1, \
.cra_ctxsize = sizeof(struct crypto_aead *), \
.cra_alignmask = 0, \
\
.cra_priority = priority, \
\
.cra_name = "morus640", \
.cra_driver_name = driver_name, \
\
.cra_module = THIS_MODULE, \
} \
} \
}
#endif /* _CRYPTO_MORUS640_GLUE_H */

23
include/crypto/morus_common.h Normal file
View File

@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* The MORUS Authenticated-Encryption Algorithm
* Common definitions
*
* Copyright (c) 2016-2018 Ondrej Mosnacek <omosnacek@gmail.com>
* Copyright (C) 2017-2018 Red Hat, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#ifndef _CRYPTO_MORUS_COMMON_H
#define _CRYPTO_MORUS_COMMON_H
#define MORUS_BLOCK_WORDS 4
#define MORUS_STATE_BLOCKS 5
#define MORUS_NONCE_SIZE 16
#define MORUS_MAX_AUTH_SIZE 16
#endif /* _CRYPTO_MORUS_COMMON_H */

27
include/crypto/salsa20.h
View File

@@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Common values for the Salsa20 algorithm
*/
#ifndef _CRYPTO_SALSA20_H
#define _CRYPTO_SALSA20_H
#include <linux/types.h>
#define SALSA20_IV_SIZE 8
#define SALSA20_MIN_KEY_SIZE 16
#define SALSA20_MAX_KEY_SIZE 32
#define SALSA20_BLOCK_SIZE 64
struct crypto_skcipher;
struct salsa20_ctx {
u32 initial_state[16];
};
void crypto_salsa20_init(u32 *state, const struct salsa20_ctx *ctx,
const u8 *iv);
int crypto_salsa20_setkey(struct crypto_skcipher *tfm, const u8 *key,
unsigned int keysize);
#endif /* _CRYPTO_SALSA20_H */

3
include/crypto/sm4.h
View File

@@ -25,4 +25,7 @@ int crypto_sm4_set_key(struct crypto_tfm *tfm, const u8 *in_key,
int crypto_sm4_expand_key(struct crypto_sm4_ctx *ctx, const u8 *in_key,
unsigned int key_len);
void crypto_sm4_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in);
void crypto_sm4_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in);
#endif

2
include/drm/amd_asic_type.h
View File

@@ -44,8 +44,10 @@ enum amd_asic_type {
CHIP_POLARIS10,
CHIP_POLARIS11,
CHIP_POLARIS12,
CHIP_VEGAM,
CHIP_VEGA10,
CHIP_VEGA12,
CHIP_VEGA20,
CHIP_RAVEN,
CHIP_LAST,
};

2
include/drm/bridge/dw_hdmi.h
View File

@@ -151,7 +151,7 @@ struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
struct drm_encoder *encoder,
const struct dw_hdmi_plat_data *plat_data);
void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense);
void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);

18
include/drm/drmP.h
View File

@@ -97,29 +97,11 @@ struct pci_controller;
#define DRM_IF_VERSION(maj, min) (maj << 16 | min)
/**
* drm_drv_uses_atomic_modeset - check if the driver implements
* atomic_commit()
* @dev: DRM device
*
* This check is useful if drivers do not have DRIVER_ATOMIC set but
* have atomic modesetting internally implemented.
*/
static inline bool drm_drv_uses_atomic_modeset(struct drm_device *dev)
{
return dev->mode_config.funcs->atomic_commit != NULL;
}
#define DRM_SWITCH_POWER_ON 0
#define DRM_SWITCH_POWER_OFF 1
#define DRM_SWITCH_POWER_CHANGING 2
#define DRM_SWITCH_POWER_DYNAMIC_OFF 3
static inline bool drm_core_check_feature(struct drm_device *dev, int feature)
{
return dev->driver->driver_features & feature;
}
/* returns true if currently okay to sleep */
static inline bool drm_can_sleep(void)
{

14
include/drm/drm_atomic.h
View File

@@ -160,6 +160,14 @@ struct __drm_crtcs_state {
struct __drm_connnectors_state {
struct drm_connector *ptr;
struct drm_connector_state *state, *old_state, *new_state;
/**
* @out_fence_ptr:
*
* User-provided pointer which the kernel uses to return a sync_file
* file descriptor. Used by writeback connectors to signal completion of
* the writeback.
*/
s32 __user *out_fence_ptr;
};
struct drm_private_obj;
@@ -594,6 +602,9 @@ void drm_atomic_set_fence_for_plane(struct drm_plane_state *plane_state,
int __must_check
drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
struct drm_crtc *crtc);
int drm_atomic_set_writeback_fb_for_connector(
struct drm_connector_state *conn_state,
struct drm_framebuffer *fb);
int __must_check
drm_atomic_add_affected_connectors(struct drm_atomic_state *state,
struct drm_crtc *crtc);
@@ -601,9 +612,6 @@ int __must_check
drm_atomic_add_affected_planes(struct drm_atomic_state *state,
struct drm_crtc *crtc);
void
drm_atomic_clean_old_fb(struct drm_device *dev, unsigned plane_mask, int ret);
int __must_check drm_atomic_check_only(struct drm_atomic_state *state);
int __must_check drm_atomic_commit(struct drm_atomic_state *state);
int __must_check drm_atomic_nonblocking_commit(struct drm_atomic_state *state);

1
include/drm/drm_atomic_helper.h
View File

@@ -100,6 +100,7 @@ int __must_check drm_atomic_helper_swap_state(struct drm_atomic_state *state,
int drm_atomic_helper_setup_commit(struct drm_atomic_state *state,
bool nonblock);
void drm_atomic_helper_wait_for_dependencies(struct drm_atomic_state *state);
void drm_atomic_helper_fake_vblank(struct drm_atomic_state *state);
void drm_atomic_helper_commit_hw_done(struct drm_atomic_state *state);
void drm_atomic_helper_commit_cleanup_done(struct drm_atomic_state *state);

48
include/drm/drm_bridge.h
View File

@@ -97,7 +97,7 @@ struct drm_bridge_funcs {
/**
* @mode_fixup:
*
* This callback is used to validate and adjust a mode. The paramater
* This callback is used to validate and adjust a mode. The parameter
* mode is the display mode that should be fed to the next element in
* the display chain, either the final &drm_connector or the next
* &drm_bridge. The parameter adjusted_mode is the input mode the bridge
@@ -178,6 +178,22 @@ struct drm_bridge_funcs {
* then this would be &drm_encoder_helper_funcs.mode_set. The display
* pipe (i.e. clocks and timing signals) is off when this function is
* called.
*
* The adjusted_mode parameter is the mode output by the CRTC for the
* first bridge in the chain. It can be different from the mode
* parameter that contains the desired mode for the connector at the end
* of the bridges chain, for instance when the first bridge in the chain
* performs scaling. The adjusted mode is mostly useful for the first
* bridge in the chain and is likely irrelevant for the other bridges.
*
* For atomic drivers the adjusted_mode is the mode stored in
* &drm_crtc_state.adjusted_mode.
*
* NOTE:
*
* If a need arises to store and access modes adjusted for other
* locations than the connection between the CRTC and the first bridge,
* the DRM framework will have to be extended with DRM bridge states.
*/
void (*mode_set)(struct drm_bridge *bridge,
struct drm_display_mode *mode,
@@ -254,27 +270,29 @@ struct drm_bridge_timings {
/**
* struct drm_bridge - central DRM bridge control structure
* @dev: DRM device this bridge belongs to
* @encoder: encoder to which this bridge is connected
* @next: the next bridge in the encoder chain
* @of_node: device node pointer to the bridge
* @list: to keep track of all added bridges
* @timings: the timing specification for the bridge, if any (may
* be NULL)
* @funcs: control functions
* @driver_private: pointer to the bridge driver's internal context
*/
struct drm_bridge {
/** @dev: DRM device this bridge belongs to */
struct drm_device *dev;
/** @encoder: encoder to which this bridge is connected */
struct drm_encoder *encoder;
/** @next: the next bridge in the encoder chain */
struct drm_bridge *next;
#ifdef CONFIG_OF
/** @of_node: device node pointer to the bridge */
struct device_node *of_node;
#endif
/** @list: to keep track of all added bridges */
struct list_head list;
/**
* @timings:
*
* the timing specification for the bridge, if any (may be NULL)
*/
const struct drm_bridge_timings *timings;
/** @funcs: control functions */
const struct drm_bridge_funcs *funcs;
/** @driver_private: pointer to the bridge driver's internal context */
void *driver_private;
};
@@ -285,15 +303,15 @@ int drm_bridge_attach(struct drm_encoder *encoder, struct drm_bridge *bridge,
struct drm_bridge *previous);
bool drm_bridge_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
enum drm_mode_status drm_bridge_mode_valid(struct drm_bridge *bridge,
const struct drm_display_mode *mode);
void drm_bridge_disable(struct drm_bridge *bridge);
void drm_bridge_post_disable(struct drm_bridge *bridge);
void drm_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
void drm_bridge_pre_enable(struct drm_bridge *bridge);
void drm_bridge_enable(struct drm_bridge *bridge);

139
include/drm/drm_client.h Normal file
View File

@@ -0,0 +1,139 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DRM_CLIENT_H_
#define _DRM_CLIENT_H_
#include <linux/types.h>
struct drm_client_dev;
struct drm_device;
struct drm_file;
struct drm_framebuffer;
struct drm_gem_object;
struct drm_minor;
struct module;
/**
* struct drm_client_funcs - DRM client callbacks
*/
struct drm_client_funcs {
/**
* @owner: The module owner
*/
struct module *owner;
/**
* @unregister:
*
* Called when &drm_device is unregistered. The client should respond by
* releasing it's resources using drm_client_release().
*
* This callback is optional.
*/
void (*unregister)(struct drm_client_dev *client);
/**
* @restore:
*
* Called on drm_lastclose(). The first client instance in the list that
* returns zero gets the privilege to restore and no more clients are
* called. This callback is not called after @unregister has been called.
*
* This callback is optional.
*/
int (*restore)(struct drm_client_dev *client);
/**
* @hotplug:
*
* Called on drm_kms_helper_hotplug_event().
* This callback is not called after @unregister has been called.
*
* This callback is optional.
*/
int (*hotplug)(struct drm_client_dev *client);
};
/**
* struct drm_client_dev - DRM client instance
*/
struct drm_client_dev {
/**
* @dev: DRM device
*/
struct drm_device *dev;
/**
* @name: Name of the client.
*/
const char *name;
/**
* @list:
*
* List of all clients of a DRM device, linked into
* &drm_device.clientlist. Protected by &drm_device.clientlist_mutex.
*/
struct list_head list;
/**
* @funcs: DRM client functions (optional)
*/
const struct drm_client_funcs *funcs;
/**
* @file: DRM file
*/
struct drm_file *file;
};
int drm_client_new(struct drm_device *dev, struct drm_client_dev *client,
const char *name, const struct drm_client_funcs *funcs);
void drm_client_release(struct drm_client_dev *client);
void drm_client_dev_unregister(struct drm_device *dev);
void drm_client_dev_hotplug(struct drm_device *dev);
void drm_client_dev_restore(struct drm_device *dev);
/**
* struct drm_client_buffer - DRM client buffer
*/
struct drm_client_buffer {
/**
* @client: DRM client
*/
struct drm_client_dev *client;
/**
* @handle: Buffer handle
*/
u32 handle;
/**
* @pitch: Buffer pitch
*/
u32 pitch;
/**
* @gem: GEM object backing this buffer
*/
struct drm_gem_object *gem;
/**
* @vaddr: Virtual address for the buffer
*/
void *vaddr;
/**
* @fb: DRM framebuffer
*/
struct drm_framebuffer *fb;
};
struct drm_client_buffer *
drm_client_framebuffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format);
void drm_client_framebuffer_delete(struct drm_client_buffer *buffer);
int drm_client_debugfs_init(struct drm_minor *minor);
#endif

279
include/drm/drm_connector.h
View File

@@ -290,6 +290,10 @@ struct drm_display_info {
#define DRM_BUS_FLAG_DATA_MSB_TO_LSB (1<<4)
/* data is transmitted LSB to MSB on the bus */
#define DRM_BUS_FLAG_DATA_LSB_TO_MSB (1<<5)
/* drive sync on pos. edge */
#define DRM_BUS_FLAG_SYNC_POSEDGE (1<<6)
/* drive sync on neg. edge */
#define DRM_BUS_FLAG_SYNC_NEGEDGE (1<<7)
/**
* @bus_flags: Additional information (like pixel signal polarity) for
@@ -374,12 +378,9 @@ struct drm_tv_connector_state {
/**
* struct drm_connector_state - mutable connector state
* @connector: backpointer to the connector
* @best_encoder: can be used by helpers and drivers to select the encoder
* @state: backpointer to global drm_atomic_state
* @tv: TV connector state
*/
struct drm_connector_state {
/** @connector: backpointer to the connector */
struct drm_connector *connector;
/**
@@ -390,6 +391,13 @@ struct drm_connector_state {
*/
struct drm_crtc *crtc;
/**
* @best_encoder:
*
* Used by the atomic helpers to select the encoder, through the
* &drm_connector_helper_funcs.atomic_best_encoder or
* &drm_connector_helper_funcs.best_encoder callbacks.
*/
struct drm_encoder *best_encoder;
/**
@@ -398,6 +406,7 @@ struct drm_connector_state {
*/
enum drm_link_status link_status;
/** @state: backpointer to global drm_atomic_state */
struct drm_atomic_state *state;
/**
@@ -407,6 +416,7 @@ struct drm_connector_state {
*/
struct drm_crtc_commit *commit;
/** @tv: TV connector state */
struct drm_tv_connector_state tv;
/**
@@ -418,6 +428,14 @@ struct drm_connector_state {
*/
enum hdmi_picture_aspect picture_aspect_ratio;
/**
* @content_type: Connector property to control the
* HDMI infoframe content type setting.
* The %DRM_MODE_CONTENT_TYPE_\* values much
* match the values.
*/
unsigned int content_type;
/**
* @scaling_mode: Connector property to control the
* upscaling, mostly used for built-in panels.
@@ -429,6 +447,19 @@ struct drm_connector_state {
* protection. This is most commonly used for HDCP.
*/
unsigned int content_protection;
/**
* @writeback_job: Writeback job for writeback connectors
*
* Holds the framebuffer and out-fence for a writeback connector. As
* the writeback completion may be asynchronous to the normal commit
* cycle, the writeback job lifetime is managed separately from the
* normal atomic state by this object.
*
* See also: drm_writeback_queue_job() and
* drm_writeback_signal_completion()
*/
struct drm_writeback_job *writeback_job;
};
/**
@@ -530,8 +561,7 @@ struct drm_connector_funcs {
* received for this output connector->edid must be NULL.
*
* Drivers using the probe helpers should use
* drm_helper_probe_single_connector_modes() or
* drm_helper_probe_single_connector_modes_nomerge() to implement this
* drm_helper_probe_single_connector_modes() to implement this
* function.
*
* RETURNS:
@@ -608,6 +638,8 @@ struct drm_connector_funcs {
* cleaned up by calling the @atomic_destroy_state hook in this
* structure.
*
* This callback is mandatory for atomic drivers.
*
* Atomic drivers which don't subclass &struct drm_connector_state should use
* drm_atomic_helper_connector_duplicate_state(). Drivers that subclass the
* state structure to extend it with driver-private state should use
@@ -634,6 +666,8 @@ struct drm_connector_funcs {
*
* Destroy a state duplicated with @atomic_duplicate_state and release
* or unreference all resources it references
*
* This callback is mandatory for atomic drivers.
*/
void (*atomic_destroy_state)(struct drm_connector *connector,
struct drm_connector_state *state);
@@ -738,45 +772,6 @@ struct drm_cmdline_mode {
/**
* struct drm_connector - central DRM connector control structure
* @dev: parent DRM device
* @kdev: kernel device for sysfs attributes
* @attr: sysfs attributes
* @head: list management
* @base: base KMS object
* @name: human readable name, can be overwritten by the driver
* @connector_type: one of the DRM_MODE_CONNECTOR_<foo> types from drm_mode.h
* @connector_type_id: index into connector type enum
* @interlace_allowed: can this connector handle interlaced modes?
* @doublescan_allowed: can this connector handle doublescan?
* @stereo_allowed: can this connector handle stereo modes?
* @funcs: connector control functions
* @edid_blob_ptr: DRM property containing EDID if present
* @properties: property tracking for this connector
* @dpms: current dpms state
* @helper_private: mid-layer private data
* @cmdline_mode: mode line parsed from the kernel cmdline for this connector
* @force: a DRM_FORCE_<foo> state for forced mode sets
* @override_edid: has the EDID been overwritten through debugfs for testing?
* @encoder_ids: valid encoders for this connector
* @eld: EDID-like data, if present
* @latency_present: AV delay info from ELD, if found
* @video_latency: video latency info from ELD, if found
* @audio_latency: audio latency info from ELD, if found
* @null_edid_counter: track sinks that give us all zeros for the EDID
* @bad_edid_counter: track sinks that give us an EDID with invalid checksum
* @edid_corrupt: indicates whether the last read EDID was corrupt
* @debugfs_entry: debugfs directory for this connector
* @has_tile: is this connector connected to a tiled monitor
* @tile_group: tile group for the connected monitor
* @tile_is_single_monitor: whether the tile is one monitor housing
* @num_h_tile: number of horizontal tiles in the tile group
* @num_v_tile: number of vertical tiles in the tile group
* @tile_h_loc: horizontal location of this tile
* @tile_v_loc: vertical location of this tile
* @tile_h_size: horizontal size of this tile.
* @tile_v_size: vertical size of this tile.
* @scaling_mode_property: Optional atomic property to control the upscaling.
* @content_protection_property: Optional property to control content protection
*
* Each connector may be connected to one or more CRTCs, or may be clonable by
* another connector if they can share a CRTC. Each connector also has a specific
@@ -784,13 +779,27 @@ struct drm_cmdline_mode {
* span multiple monitors).
*/
struct drm_connector {
/** @dev: parent DRM device */
struct drm_device *dev;
/** @kdev: kernel device for sysfs attributes */
struct device *kdev;
/** @attr: sysfs attributes */
struct device_attribute *attr;
/**
* @head:
*
* List of all connectors on a @dev, linked from
* &drm_mode_config.connector_list. Protected by
* &drm_mode_config.connector_list_lock, but please only use
* &drm_connector_list_iter to walk this list.
*/
struct list_head head;
/** @base: base KMS object */
struct drm_mode_object base;
/** @name: human readable name, can be overwritten by the driver */
char *name;
/**
@@ -808,10 +817,30 @@ struct drm_connector {
*/
unsigned index;
/**
* @connector_type:
* one of the DRM_MODE_CONNECTOR_<foo> types from drm_mode.h
*/
int connector_type;
/** @connector_type_id: index into connector type enum */
int connector_type_id;
/**
* @interlace_allowed:
* Can this connector handle interlaced modes? Only used by
* drm_helper_probe_single_connector_modes() for mode filtering.
*/
bool interlace_allowed;
/**
* @doublescan_allowed:
* Can this connector handle doublescan? Only used by
* drm_helper_probe_single_connector_modes() for mode filtering.
*/
bool doublescan_allowed;
/**
* @stereo_allowed:
* Can this connector handle stereo modes? Only used by
* drm_helper_probe_single_connector_modes() for mode filtering.
*/
bool stereo_allowed;
/**
@@ -860,45 +889,42 @@ struct drm_connector {
* Protected by &drm_mode_config.mutex.
*/
struct drm_display_info display_info;
/** @funcs: connector control functions */
const struct drm_connector_funcs *funcs;
/**
* @edid_blob_ptr: DRM property containing EDID if present. Protected by
* &drm_mode_config.mutex. This should be updated only by calling
* drm_connector_update_edid_property().
*/
struct drm_property_blob *edid_blob_ptr;
/** @properties: property tracking for this connector */
struct drm_object_properties properties;
/**
* @scaling_mode_property: Optional atomic property to control the
* upscaling. See drm_connector_attach_content_protection_property().
*/
struct drm_property *scaling_mode_property;
/**
* @content_protection_property: DRM ENUM property for content
* protection
* protection. See drm_connector_attach_content_protection_property().
*/
struct drm_property *content_protection_property;
/**
* @path_blob_ptr:
*
* DRM blob property data for the DP MST path property.
* DRM blob property data for the DP MST path property. This should only
* be updated by calling drm_connector_set_path_property().
*/
struct drm_property_blob *path_blob_ptr;
/**
* @tile_blob_ptr:
*
* DRM blob property data for the tile property (used mostly by DP MST).
* This is meant for screens which are driven through separate display
* pipelines represented by &drm_crtc, which might not be running with
* genlocked clocks. For tiled panels which are genlocked, like
* dual-link LVDS or dual-link DSI, the driver should try to not expose
* the tiling and virtualize both &drm_crtc and &drm_plane if needed.
*/
struct drm_property_blob *tile_blob_ptr;
/* should we poll this connector for connects and disconnects */
/* hot plug detectable */
#define DRM_CONNECTOR_POLL_HPD (1 << 0)
/* poll for connections */
#define DRM_CONNECTOR_POLL_CONNECT (1 << 1)
/* can cleanly poll for disconnections without flickering the screen */
/* DACs should rarely do this without a lot of testing */
#define DRM_CONNECTOR_POLL_DISCONNECT (1 << 2)
/**
@@ -915,25 +941,40 @@ struct drm_connector {
* Periodically poll the connector for connection.
*
* DRM_CONNECTOR_POLL_DISCONNECT
* Periodically poll the connector for disconnection.
* Periodically poll the connector for disconnection, without
* causing flickering even when the connector is in use. DACs should
* rarely do this without a lot of testing.
*
* Set to 0 for connectors that don't support connection status
* discovery.
*/
uint8_t polled;
/* requested DPMS state */
/**
* @dpms: Current dpms state. For legacy drivers the
* &drm_connector_funcs.dpms callback must update this. For atomic
* drivers, this is handled by the core atomic code, and drivers must
* only take &drm_crtc_state.active into account.
*/
int dpms;
/** @helper_private: mid-layer private data */
const struct drm_connector_helper_funcs *helper_private;
/* forced on connector */
/** @cmdline_mode: mode line parsed from the kernel cmdline for this connector */
struct drm_cmdline_mode cmdline_mode;
/** @force: a DRM_FORCE_<foo> state for forced mode sets */
enum drm_connector_force force;
/** @override_edid: has the EDID been overwritten through debugfs for testing? */
bool override_edid;
#define DRM_CONNECTOR_MAX_ENCODER 3
/**
* @encoder_ids: Valid encoders for this connector. Please only use
* drm_connector_for_each_possible_encoder() to enumerate these.
*/
uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER];
/**
* @encoder: Currently bound encoder driving this connector, if any.
* Only really meaningful for non-atomic drivers. Atomic drivers should
@@ -943,19 +984,37 @@ struct drm_connector {
struct drm_encoder *encoder;
#define MAX_ELD_BYTES 128
/* EDID bits */
/** @eld: EDID-like data, if present */
uint8_t eld[MAX_ELD_BYTES];
/** @latency_present: AV delay info from ELD, if found */
bool latency_present[2];
int video_latency[2]; /* [0]: progressive, [1]: interlaced */
/**
* @video_latency: Video latency info from ELD, if found.
* [0]: progressive, [1]: interlaced
*/
int video_latency[2];
/**
* @audio_latency: audio latency info from ELD, if found
* [0]: progressive, [1]: interlaced
*/
int audio_latency[2];
int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */
/**
* @null_edid_counter: track sinks that give us all zeros for the EDID.
* Needed to workaround some HW bugs where we get all 0s
*/
int null_edid_counter;
/** @bad_edid_counter: track sinks that give us an EDID with invalid checksum */
unsigned bad_edid_counter;
/* Flag for raw EDID header corruption - used in Displayport
* compliance testing - * Displayport Link CTS Core 1.2 rev1.1 4.2.2.6
/**
* @edid_corrupt: Indicates whether the last read EDID was corrupt. Used
* in Displayport compliance testing - Displayport Link CTS Core 1.2
* rev1.1 4.2.2.6
*/
bool edid_corrupt;
/** @debugfs_entry: debugfs directory for this connector */
struct dentry *debugfs_entry;
/**
@@ -963,7 +1022,7 @@ struct drm_connector {
*
* Current atomic state for this connector.
*
* This is protected by @drm_mode_config.connection_mutex. Note that
* This is protected by &drm_mode_config.connection_mutex. Note that
* nonblocking atomic commits access the current connector state without
* taking locks. Either by going through the &struct drm_atomic_state
* pointers, see for_each_oldnew_connector_in_state(),
@@ -974,19 +1033,44 @@ struct drm_connector {
*/
struct drm_connector_state *state;
/* DisplayID bits */
/* DisplayID bits. FIXME: Extract into a substruct? */
/**
* @tile_blob_ptr:
*
* DRM blob property data for the tile property (used mostly by DP MST).
* This is meant for screens which are driven through separate display
* pipelines represented by &drm_crtc, which might not be running with
* genlocked clocks. For tiled panels which are genlocked, like
* dual-link LVDS or dual-link DSI, the driver should try to not expose
* the tiling and virtualize both &drm_crtc and &drm_plane if needed.
*
* This should only be updated by calling
* drm_connector_set_tile_property().
*/
struct drm_property_blob *tile_blob_ptr;
/** @has_tile: is this connector connected to a tiled monitor */
bool has_tile;
/** @tile_group: tile group for the connected monitor */
struct drm_tile_group *tile_group;
/** @tile_is_single_monitor: whether the tile is one monitor housing */
bool tile_is_single_monitor;
/** @num_h_tile: number of horizontal tiles in the tile group */
/** @num_v_tile: number of vertical tiles in the tile group */
uint8_t num_h_tile, num_v_tile;
/** @tile_h_loc: horizontal location of this tile */
/** @tile_v_loc: vertical location of this tile */
uint8_t tile_h_loc, tile_v_loc;
/** @tile_h_size: horizontal size of this tile. */
/** @tile_v_size: vertical size of this tile. */
uint16_t tile_h_size, tile_v_size;
/**
* @free_node:
*
* List used only by &drm_connector_iter to be able to clean up a
* List used only by &drm_connector_list_iter to be able to clean up a
* connector from any context, in conjunction with
* &drm_mode_config.connector_free_work.
*/
@@ -1001,15 +1085,21 @@ int drm_connector_init(struct drm_device *dev,
int connector_type);
int drm_connector_register(struct drm_connector *connector);
void drm_connector_unregister(struct drm_connector *connector);
int drm_mode_connector_attach_encoder(struct drm_connector *connector,
int drm_connector_attach_encoder(struct drm_connector *connector,
struct drm_encoder *encoder);
void drm_connector_cleanup(struct drm_connector *connector);
static inline unsigned drm_connector_index(struct drm_connector *connector)
static inline unsigned int drm_connector_index(const struct drm_connector *connector)
{
return connector->index;
}
static inline u32 drm_connector_mask(const struct drm_connector *connector)
{
return 1 << connector->index;
}
/**
* drm_connector_lookup - lookup connector object
* @dev: DRM device
@@ -1089,20 +1179,25 @@ int drm_mode_create_tv_properties(struct drm_device *dev,
unsigned int num_modes,
const char * const modes[]);
int drm_mode_create_scaling_mode_property(struct drm_device *dev);
int drm_connector_attach_content_type_property(struct drm_connector *dev);
int drm_connector_attach_scaling_mode_property(struct drm_connector *connector,
u32 scaling_mode_mask);
int drm_connector_attach_content_protection_property(
struct drm_connector *connector);
int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
int drm_mode_create_content_type_property(struct drm_device *dev);
void drm_hdmi_avi_infoframe_content_type(struct hdmi_avi_infoframe *frame,
const struct drm_connector_state *conn_state);
int drm_mode_create_suggested_offset_properties(struct drm_device *dev);
int drm_mode_connector_set_path_property(struct drm_connector *connector,
const char *path);
int drm_mode_connector_set_tile_property(struct drm_connector *connector);
int drm_mode_connector_update_edid_property(struct drm_connector *connector,
const struct edid *edid);
void drm_mode_connector_set_link_status_property(struct drm_connector *connector,
uint64_t link_status);
int drm_connector_set_path_property(struct drm_connector *connector,
const char *path);
int drm_connector_set_tile_property(struct drm_connector *connector);
int drm_connector_update_edid_property(struct drm_connector *connector,
const struct edid *edid);
void drm_connector_set_link_status_property(struct drm_connector *connector,
uint64_t link_status);
int drm_connector_init_panel_orientation_property(
struct drm_connector *connector, int width, int height);
@@ -1151,6 +1246,9 @@ struct drm_connector *
drm_connector_list_iter_next(struct drm_connector_list_iter *iter);
void drm_connector_list_iter_end(struct drm_connector_list_iter *iter);
bool drm_connector_has_possible_encoder(struct drm_connector *connector,
struct drm_encoder *encoder);
/**
* drm_for_each_connector_iter - connector_list iterator macro
* @connector: &struct drm_connector pointer used as cursor
@@ -1163,4 +1261,17 @@ void drm_connector_list_iter_end(struct drm_connector_list_iter *iter);
#define drm_for_each_connector_iter(connector, iter) \
while ((connector = drm_connector_list_iter_next(iter)))
/**
* drm_connector_for_each_possible_encoder - iterate connector's possible encoders
* @connector: &struct drm_connector pointer
* @encoder: &struct drm_encoder pointer used as cursor
* @__i: int iteration cursor, for macro-internal use
*/
#define drm_connector_for_each_possible_encoder(connector, encoder, __i) \
for ((__i) = 0; (__i) < ARRAY_SIZE((connector)->encoder_ids) && \
(connector)->encoder_ids[(__i)] != 0; (__i)++) \
for_each_if((encoder) = \
drm_encoder_find((connector)->dev, NULL, \
(connector)->encoder_ids[(__i)])) \
#endif

276
include/drm/drm_crtc.h
View File

@@ -77,21 +77,6 @@ struct drm_plane_helper_funcs;
/**
* struct drm_crtc_state - mutable CRTC state
* @crtc: backpointer to the CRTC
* @enable: whether the CRTC should be enabled, gates all other state
* @active: whether the CRTC is actively displaying (used for DPMS)
* @planes_changed: planes on this crtc are updated
* @mode_changed: @mode or @enable has been changed
* @active_changed: @active has been toggled.
* @connectors_changed: connectors to this crtc have been updated
* @zpos_changed: zpos values of planes on this crtc have been updated
* @color_mgmt_changed: color management properties have changed (degamma or
* gamma LUT or CSC matrix)
* @plane_mask: bitmask of (1 << drm_plane_index(plane)) of attached planes
* @connector_mask: bitmask of (1 << drm_connector_index(connector)) of attached connectors
* @encoder_mask: bitmask of (1 << drm_encoder_index(encoder)) of attached encoders
* @mode_blob: &drm_property_blob for @mode
* @state: backpointer to global drm_atomic_state
*
* Note that the distinction between @enable and @active is rather subtile:
* Flipping @active while @enable is set without changing anything else may
@@ -102,31 +87,127 @@ struct drm_plane_helper_funcs;
*
* The three booleans active_changed, connectors_changed and mode_changed are
* intended to indicate whether a full modeset is needed, rather than strictly
* describing what has changed in a commit.
* See also: drm_atomic_crtc_needs_modeset()
* describing what has changed in a commit. See also:
* drm_atomic_crtc_needs_modeset()
*
* WARNING: Transitional helpers (like drm_helper_crtc_mode_set() or
* drm_helper_crtc_mode_set_base()) do not maintain many of the derived control
* state like @plane_mask so drivers not converted over to atomic helpers should
* not rely on these being accurate!
*/
struct drm_crtc_state {
/** @crtc: backpointer to the CRTC */
struct drm_crtc *crtc;
/**
* @enable: Whether the CRTC should be enabled, gates all other state.
* This controls reservations of shared resources. Actual hardware state
* is controlled by @active.
*/
bool enable;
/**
* @active: Whether the CRTC is actively displaying (used for DPMS).
* Implies that @enable is set. The driver must not release any shared
* resources if @active is set to false but @enable still true, because
* userspace expects that a DPMS ON always succeeds.
*
* Hence drivers must not consult @active in their various
* &drm_mode_config_funcs.atomic_check callback to reject an atomic
* commit. They can consult it to aid in the computation of derived
* hardware state, since even in the DPMS OFF state the display hardware
* should be as much powered down as when the CRTC is completely
* disabled through setting @enable to false.
*/
bool active;
/* computed state bits used by helpers and drivers */
/**
* @planes_changed: Planes on this crtc are updated. Used by the atomic
* helpers and drivers to steer the atomic commit control flow.
*/
bool planes_changed : 1;
/**
* @mode_changed: @mode or @enable has been changed. Used by the atomic
* helpers and drivers to steer the atomic commit control flow. See also
* drm_atomic_crtc_needs_modeset().
*
* Drivers are supposed to set this for any CRTC state changes that
* require a full modeset. They can also reset it to false if e.g. a
* @mode change can be done without a full modeset by only changing
* scaler settings.
*/
bool mode_changed : 1;
/**
* @active_changed: @active has been toggled. Used by the atomic
* helpers and drivers to steer the atomic commit control flow. See also
* drm_atomic_crtc_needs_modeset().
*/
bool active_changed : 1;
/**
* @connectors_changed: Connectors to this crtc have been updated,
* either in their state or routing. Used by the atomic
* helpers and drivers to steer the atomic commit control flow. See also
* drm_atomic_crtc_needs_modeset().
*
* Drivers are supposed to set this as-needed from their own atomic
* check code, e.g. from &drm_encoder_helper_funcs.atomic_check
*/
bool connectors_changed : 1;
/**
* @zpos_changed: zpos values of planes on this crtc have been updated.
* Used by the atomic helpers and drivers to steer the atomic commit
* control flow.
*/
bool zpos_changed : 1;
/**
* @color_mgmt_changed: Color management properties have changed
* (@gamma_lut, @degamma_lut or @ctm). Used by the atomic helpers and
* drivers to steer the atomic commit control flow.
*/
bool color_mgmt_changed : 1;
/* attached planes bitmask:
* WARNING: transitional helpers do not maintain plane_mask so
* drivers not converted over to atomic helpers should not rely
* on plane_mask being accurate!
/**
* @no_vblank:
*
* Reflects the ability of a CRTC to send VBLANK events. This state
* usually depends on the pipeline configuration, and the main usuage
* is CRTCs feeding a writeback connector operating in oneshot mode.
* In this case the VBLANK event is only generated when a job is queued
* to the writeback connector, and we want the core to fake VBLANK
* events when this part of the pipeline hasn't changed but others had
* or when the CRTC and connectors are being disabled.
*
* __drm_atomic_helper_crtc_duplicate_state() will not reset the value
* from the current state, the CRTC driver is then responsible for
* updating this field when needed.
*
* Note that the combination of &drm_crtc_state.event == NULL and
* &drm_crtc_state.no_blank == true is valid and usually used when the
* writeback connector attached to the CRTC has a new job queued. In
* this case the driver will send the VBLANK event on its own when the
* writeback job is complete.
*/
bool no_vblank : 1;
/**
* @plane_mask: Bitmask of drm_plane_mask(plane) of planes attached to
* this CRTC.
*/
u32 plane_mask;
/**
* @connector_mask: Bitmask of drm_connector_mask(connector) of
* connectors attached to this CRTC.
*/
u32 connector_mask;
/**
* @encoder_mask: Bitmask of drm_encoder_mask(encoder) of encoders
* attached to this CRTC.
*/
u32 encoder_mask;
/**
@@ -134,10 +215,13 @@ struct drm_crtc_state {
*
* Internal display timings which can be used by the driver to handle
* differences between the mode requested by userspace in @mode and what
* is actually programmed into the hardware. It is purely driver
* implementation defined what exactly this adjusted mode means. Usually
* it is used to store the hardware display timings used between the
* CRTC and encoder blocks.
* is actually programmed into the hardware.
*
* For drivers using &drm_bridge, this stores hardware display timings
* used between the CRTC and the first bridge. For other drivers, the
* meaning of the adjusted_mode field is purely driver implementation
* defined information, and will usually be used to store the hardware
* display timings used between the CRTC and encoder blocks.
*/
struct drm_display_mode adjusted_mode;
@@ -158,7 +242,10 @@ struct drm_crtc_state {
*/
struct drm_display_mode mode;
/* blob property to expose current mode to atomic userspace */
/**
* @mode_blob: &drm_property_blob for @mode, for exposing the mode to
* atomic userspace.
*/
struct drm_property_blob *mode_blob;
/**
@@ -262,6 +349,7 @@ struct drm_crtc_state {
*/
struct drm_crtc_commit *commit;
/** @state: backpointer to global drm_atomic_state */
struct drm_atomic_state *state;
};
@@ -503,6 +591,8 @@ struct drm_crtc_funcs {
* cleaned up by calling the @atomic_destroy_state hook in this
* structure.
*
* This callback is mandatory for atomic drivers.
*
* Atomic drivers which don't subclass &struct drm_crtc_state should use
* drm_atomic_helper_crtc_duplicate_state(). Drivers that subclass the
* state structure to extend it with driver-private state should use
@@ -529,6 +619,8 @@ struct drm_crtc_funcs {
*
* Destroy a state duplicated with @atomic_duplicate_state and release
* or unreference all resources it references
*
* This callback is mandatory for atomic drivers.
*/
void (*atomic_destroy_state)(struct drm_crtc *crtc,
struct drm_crtc_state *state);
@@ -717,35 +809,25 @@ struct drm_crtc_funcs {
/**
* struct drm_crtc - central CRTC control structure
* @dev: parent DRM device
* @port: OF node used by drm_of_find_possible_crtcs()
* @head: list management
* @name: human readable name, can be overwritten by the driver
* @mutex: per-CRTC locking
* @base: base KMS object for ID tracking etc.
* @primary: primary plane for this CRTC
* @cursor: cursor plane for this CRTC
* @cursor_x: current x position of the cursor, used for universal cursor planes
* @cursor_y: current y position of the cursor, used for universal cursor planes
* @enabled: is this CRTC enabled?
* @mode: current mode timings
* @hwmode: mode timings as programmed to hw regs
* @x: x position on screen
* @y: y position on screen
* @funcs: CRTC control functions
* @gamma_size: size of gamma ramp
* @gamma_store: gamma ramp values
* @helper_private: mid-layer private data
* @properties: property tracking for this CRTC
*
* Each CRTC may have one or more connectors associated with it. This structure
* allows the CRTC to be controlled.
*/
struct drm_crtc {
/** @dev: parent DRM device */
struct drm_device *dev;
/** @port: OF node used by drm_of_find_possible_crtcs(). */
struct device_node *port;
/**
* @head:
*
* List of all CRTCs on @dev, linked from &drm_mode_config.crtc_list.
* Invariant over the lifetime of @dev and therefore does not need
* locking.
*/
struct list_head head;
/** @name: human readable name, can be overwritten by the driver */
char *name;
/**
@@ -760,10 +842,25 @@ struct drm_crtc {
*/
struct drm_modeset_lock mutex;
/** @base: base KMS object for ID tracking etc. */
struct drm_mode_object base;
/* primary and cursor planes for CRTC */
/**
* @primary:
* Primary plane for this CRTC. Note that this is only
* relevant for legacy IOCTL, it specifies the plane implicitly used by
* the SETCRTC and PAGE_FLIP IOCTLs. It does not have any significance
* beyond that.
*/
struct drm_plane *primary;
/**
* @cursor:
* Cursor plane for this CRTC. Note that this is only relevant for
* legacy IOCTL, it specifies the plane implicitly used by the SETCURSOR
* and SETCURSOR2 IOCTLs. It does not have any significance
* beyond that.
*/
struct drm_plane *cursor;
/**
@@ -772,30 +869,94 @@ struct drm_crtc {
*/
unsigned index;
/* position of cursor plane on crtc */
/**
* @cursor_x: Current x position of the cursor, used for universal
* cursor planes because the SETCURSOR IOCTL only can update the
* framebuffer without supplying the coordinates. Drivers should not use
* this directly, atomic drivers should look at &drm_plane_state.crtc_x
* of the cursor plane instead.
*/
int cursor_x;
/**
* @cursor_y: Current y position of the cursor, used for universal
* cursor planes because the SETCURSOR IOCTL only can update the
* framebuffer without supplying the coordinates. Drivers should not use
* this directly, atomic drivers should look at &drm_plane_state.crtc_y
* of the cursor plane instead.
*/
int cursor_y;
/**
* @enabled:
*
* Is this CRTC enabled? Should only be used by legacy drivers, atomic
* drivers should instead consult &drm_crtc_state.enable and
* &drm_crtc_state.active. Atomic drivers can update this by calling
* drm_atomic_helper_update_legacy_modeset_state().
*/
bool enabled;
/* Requested mode from modesetting. */
/**
* @mode:
*
* Current mode timings. Should only be used by legacy drivers, atomic
* drivers should instead consult &drm_crtc_state.mode. Atomic drivers
* can update this by calling
* drm_atomic_helper_update_legacy_modeset_state().
*/
struct drm_display_mode mode;
/* Programmed mode in hw, after adjustments for encoders,
* crtc, panel scaling etc. Needed for timestamping etc.
/**
* @hwmode:
*
* Programmed mode in hw, after adjustments for encoders, crtc, panel
* scaling etc. Should only be used by legacy drivers, for high
* precision vblank timestamps in
* drm_calc_vbltimestamp_from_scanoutpos().
*
* Note that atomic drivers should not use this, but instead use
* &drm_crtc_state.adjusted_mode. And for high-precision timestamps
* drm_calc_vbltimestamp_from_scanoutpos() used &drm_vblank_crtc.hwmode,
* which is filled out by calling drm_calc_timestamping_constants().
*/
struct drm_display_mode hwmode;
int x, y;
/**
* @x:
* x position on screen. Should only be used by legacy drivers, atomic
* drivers should look at &drm_plane_state.crtc_x of the primary plane
* instead. Updated by calling
* drm_atomic_helper_update_legacy_modeset_state().
*/
int x;
/**
* @y:
* y position on screen. Should only be used by legacy drivers, atomic
* drivers should look at &drm_plane_state.crtc_y of the primary plane
* instead. Updated by calling
* drm_atomic_helper_update_legacy_modeset_state().
*/
int y;
/** @funcs: CRTC control functions */
const struct drm_crtc_funcs *funcs;
/* Legacy FB CRTC gamma size for reporting to userspace */
/**
* @gamma_size: Size of legacy gamma ramp reported to userspace. Set up
* by calling drm_mode_crtc_set_gamma_size().
*/
uint32_t gamma_size;
/**
* @gamma_store: Gamma ramp values used by the legacy SETGAMMA and
* GETGAMMA IOCTls. Set up by calling drm_mode_crtc_set_gamma_size().
*/
uint16_t *gamma_store;
/* if you are using the helper */
/** @helper_private: mid-layer private data */
const struct drm_crtc_helper_funcs *helper_private;
/** @properties: property tracking for this CRTC */
struct drm_object_properties properties;
/**
@@ -865,7 +1026,6 @@ struct drm_crtc {
*
* spinlock to protect the fences in the fence_context.
*/
spinlock_t fence_lock;
/**
* @fence_seqno:
@@ -935,8 +1095,8 @@ static inline unsigned int drm_crtc_index(const struct drm_crtc *crtc)
* drm_crtc_mask - find the mask of a registered CRTC
* @crtc: CRTC to find mask for
*
* Given a registered CRTC, return the mask bit of that CRTC for an
* encoder's possible_crtcs field.
* Given a registered CRTC, return the mask bit of that CRTC for the
* &drm_encoder.possible_crtcs and &drm_plane.possible_crtcs fields.
*/
static inline uint32_t drm_crtc_mask(const struct drm_crtc *crtc)
{

3
include/drm/drm_debugfs_crc.h
View File

@@ -43,6 +43,7 @@ struct drm_crtc_crc_entry {
* @lock: protects the fields in this struct
* @source: name of the currently configured source of CRCs
* @opened: whether userspace has opened the data file for reading
* @overflow: whether an overflow occured.
* @entries: array of entries, with size of %DRM_CRC_ENTRIES_NR
* @head: head of circular queue
* @tail: tail of circular queue
@@ -52,7 +53,7 @@ struct drm_crtc_crc_entry {
struct drm_crtc_crc {
spinlock_t lock;
const char *source;
bool opened;
bool opened, overflow;
struct drm_crtc_crc_entry *entries;
int head, tail;
size_t values_cnt;

22
include/drm/drm_device.h
View File

@@ -38,7 +38,6 @@ struct drm_device {
struct device *dev; /**< Device structure of bus-device */
struct drm_driver *driver; /**< DRM driver managing the device */
void *dev_private; /**< DRM driver private data */
struct drm_minor *control; /**< Control node */
struct drm_minor *primary; /**< Primary node */
struct drm_minor *render; /**< Render node */
bool registered;
@@ -75,6 +74,27 @@ struct drm_device {
struct mutex filelist_mutex;
struct list_head filelist;
/**
* @filelist_internal:
*
* List of open DRM files for in-kernel clients. Protected by @filelist_mutex.
*/
struct list_head filelist_internal;
/**
* @clientlist_mutex:
*
* Protects @clientlist access.
*/
struct mutex clientlist_mutex;
/**
* @clientlist:
*
* List of in-kernel clients. Protected by @clientlist_mutex.
*/
struct list_head clientlist;
/** \name Memory management */
/*@{ */
struct list_head maplist; /**< Linked list of regions */

70
include/drm/drm_dp_helper.h
View File

@@ -64,6 +64,11 @@
/* AUX CH addresses */
/* DPCD */
#define DP_DPCD_REV 0x000
# define DP_DPCD_REV_10 0x10
# define DP_DPCD_REV_11 0x11
# define DP_DPCD_REV_12 0x12
# define DP_DPCD_REV_13 0x13
# define DP_DPCD_REV_14 0x14
#define DP_MAX_LINK_RATE 0x001
@@ -119,6 +124,7 @@
# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
@@ -977,18 +983,18 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw);
#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
/* 0x80+ CEA-861 infoframe types */
struct edp_sdp_header {
struct dp_sdp_header {
u8 HB0; /* Secondary Data Packet ID */
u8 HB1; /* Secondary Data Packet Type */
u8 HB2; /* 7:5 reserved, 4:0 revision number */
u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
u8 HB2; /* Secondary Data Packet Specific header, Byte 0 */
u8 HB3; /* Secondary Data packet Specific header, Byte 1 */
} __packed;
#define EDP_SDP_HEADER_REVISION_MASK 0x1F
#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
struct edp_vsc_psr {
struct edp_sdp_header sdp_header;
struct dp_sdp_header sdp_header;
u8 DB0; /* Stereo Interface */
u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
@@ -1072,6 +1078,25 @@ struct drm_dp_aux_msg {
size_t size;
};
struct cec_adapter;
struct edid;
/**
* struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
* @lock: mutex protecting this struct
* @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
* @name: name of the CEC adapter
* @parent: parent device of the CEC adapter
* @unregister_work: unregister the CEC adapter
*/
struct drm_dp_aux_cec {
struct mutex lock;
struct cec_adapter *adap;
const char *name;
struct device *parent;
struct delayed_work unregister_work;
};
/**
* struct drm_dp_aux - DisplayPort AUX channel
* @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
@@ -1130,6 +1155,10 @@ struct drm_dp_aux {
* @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
*/
unsigned i2c_defer_count;
/**
* @cec: struct containing fields used for CEC-Tunneling-over-AUX.
*/
struct drm_dp_aux_cec cec;
};
ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
@@ -1252,4 +1281,37 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
return desc->quirks & BIT(quirk);
}
#ifdef CONFIG_DRM_DP_CEC
void drm_dp_cec_irq(struct drm_dp_aux *aux);
void drm_dp_cec_register_connector(struct drm_dp_aux *aux, const char *name,
struct device *parent);
void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
#else
static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
{
}
static inline void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
const char *name,
struct device *parent)
{
}
static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
{
}
static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
const struct edid *edid)
{
}
static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
{
}
#endif
#endif /* _DRM_DP_HELPER_H_ */

29
include/drm/drm_drv.h
View File

@@ -649,6 +649,35 @@ static inline bool drm_dev_is_unplugged(struct drm_device *dev)
return true;
}
/**
* drm_core_check_feature - check driver feature flags
* @dev: DRM device to check
* @feature: feature flag
*
* This checks @dev for driver features, see &drm_driver.driver_features and the
* various DRIVER_\* flags.
*
* Returns true if the @feature is supported, false otherwise.
*/
static inline bool drm_core_check_feature(struct drm_device *dev, int feature)
{
return dev->driver->driver_features & feature;
}
/**
* drm_drv_uses_atomic_modeset - check if the driver implements
* atomic_commit()
* @dev: DRM device
*
* This check is useful if drivers do not have DRIVER_ATOMIC set but
* have atomic modesetting internally implemented.
*/
static inline bool drm_drv_uses_atomic_modeset(struct drm_device *dev)
{
return drm_core_check_feature(dev, DRIVER_ATOMIC) ||
dev->mode_config.funcs->atomic_commit != NULL;
}
int drm_dev_set_unique(struct drm_device *dev, const char *name);

16
include/drm/drm_encoder.h
View File

@@ -191,11 +191,23 @@ int drm_encoder_init(struct drm_device *dev,
* Given a registered encoder, return the index of that encoder within a DRM
* device's list of encoders.
*/
static inline unsigned int drm_encoder_index(struct drm_encoder *encoder)
static inline unsigned int drm_encoder_index(const struct drm_encoder *encoder)
{
return encoder->index;
}
/**
* drm_encoder_mask - find the mask of a registered ENCODER
* @encoder: encoder to find mask for
*
* Given a registered encoder, return the mask bit of that encoder for an
* encoder's possible_clones field.
*/
static inline u32 drm_encoder_mask(const struct drm_encoder *encoder)
{
return 1 << drm_encoder_index(encoder);
}
/**
* drm_encoder_crtc_ok - can a given crtc drive a given encoder?
* @encoder: encoder to test
@@ -241,7 +253,7 @@ void drm_encoder_cleanup(struct drm_encoder *encoder);
*/
#define drm_for_each_encoder_mask(encoder, dev, encoder_mask) \
list_for_each_entry((encoder), &(dev)->mode_config.encoder_list, head) \
for_each_if ((encoder_mask) & (1 << drm_encoder_index(encoder)))
for_each_if ((encoder_mask) & drm_encoder_mask(encoder))
/**
* drm_for_each_encoder - iterate over all encoders

6
include/drm/drm_fb_cma_helper.h
View File

@@ -16,16 +16,10 @@ struct drm_mode_fb_cmd2;
struct drm_plane;
struct drm_plane_state;
int drm_fb_cma_fbdev_init_with_funcs(struct drm_device *dev,
unsigned int preferred_bpp, unsigned int max_conn_count,
const struct drm_framebuffer_funcs *funcs);
int drm_fb_cma_fbdev_init(struct drm_device *dev, unsigned int preferred_bpp,
unsigned int max_conn_count);
void drm_fb_cma_fbdev_fini(struct drm_device *dev);
struct drm_fbdev_cma *drm_fbdev_cma_init_with_funcs(struct drm_device *dev,
unsigned int preferred_bpp, unsigned int max_conn_count,
const struct drm_framebuffer_funcs *funcs);
struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device *dev,
unsigned int preferred_bpp, unsigned int max_conn_count);
void drm_fbdev_cma_fini(struct drm_fbdev_cma *fbdev_cma);

38
include/drm/drm_fb_helper.h
View File

@@ -32,6 +32,7 @@
struct drm_fb_helper;
#include <drm/drm_client.h>
#include <drm/drm_crtc.h>
#include <drm/drm_device.h>
#include <linux/kgdb.h>
@@ -154,6 +155,20 @@ struct drm_fb_helper_connector {
* operations.
*/
struct drm_fb_helper {
/**
* @client:
*
* DRM client used by the generic fbdev emulation.
*/
struct drm_client_dev client;
/**
* @buffer:
*
* Framebuffer used by the generic fbdev emulation.
*/
struct drm_client_buffer *buffer;
struct drm_framebuffer *fb;
struct drm_device *dev;
int crtc_count;
@@ -234,6 +249,12 @@ struct drm_fb_helper {
int preferred_bpp;
};
static inline struct drm_fb_helper *
drm_fb_helper_from_client(struct drm_client_dev *client)
{
return container_of(client, struct drm_fb_helper, client);
}
/**
* define DRM_FB_HELPER_DEFAULT_OPS - helper define for drm drivers
*
@@ -330,6 +351,10 @@ void drm_fb_helper_fbdev_teardown(struct drm_device *dev);
void drm_fb_helper_lastclose(struct drm_device *dev);
void drm_fb_helper_output_poll_changed(struct drm_device *dev);
int drm_fb_helper_generic_probe(struct drm_fb_helper *fb_helper,
struct drm_fb_helper_surface_size *sizes);
int drm_fbdev_generic_setup(struct drm_device *dev, unsigned int preferred_bpp);
#else
static inline void drm_fb_helper_prepare(struct drm_device *dev,
struct drm_fb_helper *helper,
@@ -564,6 +589,19 @@ static inline void drm_fb_helper_output_poll_changed(struct drm_device *dev)
{
}
static inline int
drm_fb_helper_generic_probe(struct drm_fb_helper *fb_helper,
struct drm_fb_helper_surface_size *sizes)
{
return 0;
}
static inline int
drm_fbdev_generic_setup(struct drm_device *dev, unsigned int preferred_bpp)
{
return 0;
}
#endif
static inline int

30
include/drm/drm_file.h
View File

@@ -47,6 +47,9 @@ struct device;
* header include loops we need it here for now.
*/
/* Note that the order of this enum is ABI (it determines
* /dev/dri/renderD* numbers).
*/
enum drm_minor_type {
DRM_MINOR_PRIMARY,
DRM_MINOR_CONTROL,
@@ -181,6 +184,21 @@ struct drm_file {
/** @atomic: True if client understands atomic properties. */
unsigned atomic:1;
/**
* @aspect_ratio_allowed:
*
* True, if client can handle picture aspect ratios, and has requested
* to pass this information along with the mode.
*/
unsigned aspect_ratio_allowed:1;
/**
* @writeback_connectors:
*
* True if client understands writeback connectors
*/
unsigned writeback_connectors:1;
/**
* @is_master:
*
@@ -348,18 +366,6 @@ static inline bool drm_is_render_client(const struct drm_file *file_priv)
return file_priv->minor->type == DRM_MINOR_RENDER;
}
/**
* drm_is_control_client - is this an open file of the control node
* @file_priv: DRM file
*
* Control nodes are deprecated and in the process of getting removed from the
* DRM userspace API. Do not ever use!
*/
static inline bool drm_is_control_client(const struct drm_file *file_priv)
{
return file_priv->minor->type == DRM_MINOR_CONTROL;
}
int drm_open(struct inode *inode, struct file *filp);
ssize_t drm_read(struct file *filp, char __user *buffer,
size_t count, loff_t *offset);

2
include/drm/drm_fourcc.h
View File

@@ -39,6 +39,7 @@ struct drm_mode_fb_cmd2;
* @hsub: Horizontal chroma subsampling factor
* @vsub: Vertical chroma subsampling factor
* @has_alpha: Does the format embeds an alpha component?
* @is_yuv: Is it a YUV format?
*/
struct drm_format_info {
u32 format;
@@ -48,6 +49,7 @@ struct drm_format_info {
u8 hsub;
u8 vsub;
bool has_alpha;
bool is_yuv;
};
/**

7
include/drm/drm_ioctl.h
View File

@@ -108,13 +108,6 @@ enum drm_ioctl_flags {
* This is equivalent to callers with the SYSADMIN capability.
*/
DRM_ROOT_ONLY = BIT(2),
/**
* @DRM_CONTROL_ALLOW:
*
* Deprecated, do not use. Control nodes are in the process of getting
* removed.
*/
DRM_CONTROL_ALLOW = BIT(3),
/**
* @DRM_UNLOCKED:
*

34
include/drm/drm_mm.h
View File

@@ -109,6 +109,38 @@ enum drm_mm_insert_mode {
* Allocates the node from the bottom of the found hole.
*/
DRM_MM_INSERT_EVICT,
/**
* @DRM_MM_INSERT_ONCE:
*
* Only check the first hole for suitablity and report -ENOSPC
* immediately otherwise, rather than check every hole until a
* suitable one is found. Can only be used in conjunction with another
* search method such as DRM_MM_INSERT_HIGH or DRM_MM_INSERT_LOW.
*/
DRM_MM_INSERT_ONCE = BIT(31),
/**
* @DRM_MM_INSERT_HIGHEST:
*
* Only check the highest hole (the hole with the largest address) and
* insert the node at the top of the hole or report -ENOSPC if
* unsuitable.
*
* Does not search all holes.
*/
DRM_MM_INSERT_HIGHEST = DRM_MM_INSERT_HIGH | DRM_MM_INSERT_ONCE,
/**
* @DRM_MM_INSERT_LOWEST:
*
* Only check the lowest hole (the hole with the smallest address) and
* insert the node at the bottom of the hole or report -ENOSPC if
* unsuitable.
*
* Does not search all holes.
*/
DRM_MM_INSERT_LOWEST = DRM_MM_INSERT_LOW | DRM_MM_INSERT_ONCE,
};
/**
@@ -173,7 +205,7 @@ struct drm_mm {
struct drm_mm_node head_node;
/* Keep an interval_tree for fast lookup of drm_mm_nodes by address. */
struct rb_root_cached interval_tree;
struct rb_root holes_size;
struct rb_root_cached holes_size;
struct rb_root holes_addr;
unsigned long scan_active;

36
include/drm/drm_mode_config.h
View File

@@ -329,10 +329,10 @@ struct drm_mode_config_funcs {
/**
* struct drm_mode_config - Mode configuration control structure
* @min_width: minimum pixel width on this device
* @min_height: minimum pixel height on this device
* @max_width: maximum pixel width on this device
* @max_height: maximum pixel height on this device
* @min_width: minimum fb pixel width on this device
* @min_height: minimum fb pixel height on this device
* @max_width: maximum fb pixel width on this device
* @max_height: maximum fb pixel height on this device
* @funcs: core driver provided mode setting functions
* @fb_base: base address of the framebuffer
* @poll_enabled: track polling support for this device
@@ -726,6 +726,11 @@ struct drm_mode_config {
* HDMI infoframe aspect ratio setting.
*/
struct drm_property *aspect_ratio_property;
/**
* @content_type_property: Optional connector property to control the
* HDMI infoframe content type setting.
*/
struct drm_property *content_type_property;
/**
* @degamma_lut_property: Optional CRTC property to set the LUT used to
* convert the framebuffer's colors to linear gamma.
@@ -779,6 +784,29 @@ struct drm_mode_config {
*/
struct drm_property *panel_orientation_property;
/**
* @writeback_fb_id_property: Property for writeback connectors, storing
* the ID of the output framebuffer.
* See also: drm_writeback_connector_init()
*/
struct drm_property *writeback_fb_id_property;
/**
* @writeback_pixel_formats_property: Property for writeback connectors,
* storing an array of the supported pixel formats for the writeback
* engine (read-only).
* See also: drm_writeback_connector_init()
*/
struct drm_property *writeback_pixel_formats_property;
/**
* @writeback_out_fence_ptr_property: Property for writeback connectors,
* fd pointer representing the outgoing fences for a writeback
* connector. Userspace should provide a pointer to a value of type s32,
* and then cast that pointer to u64.
* See also: drm_writeback_connector_init()
*/
struct drm_property *writeback_out_fence_ptr_property;
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;

24
include/drm/drm_modes.h
View File

@@ -147,6 +147,12 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
#define DRM_MODE_MATCH_TIMINGS (1 << 0)
#define DRM_MODE_MATCH_CLOCK (1 << 1)
#define DRM_MODE_MATCH_FLAGS (1 << 2)
#define DRM_MODE_MATCH_3D_FLAGS (1 << 3)
#define DRM_MODE_MATCH_ASPECT_RATIO (1 << 4)
/**
* struct drm_display_mode - DRM kernel-internal display mode structure
* @hdisplay: horizontal display size
@@ -405,6 +411,19 @@ struct drm_display_mode {
* Field for setting the HDMI picture aspect ratio of a mode.
*/
enum hdmi_picture_aspect picture_aspect_ratio;
/**
* @export_head:
*
* struct list_head for modes to be exposed to the userspace.
* This is to maintain a list of exposed modes while preparing
* user-mode's list in drm_mode_getconnector ioctl. The purpose of this
* list_head only lies in the ioctl function, and is not expected to be
* used outside the function.
* Once used, the stale pointers are not reset, but left as it is, to
* avoid overhead of protecting it by mode_config.mutex.
*/
struct list_head export_head;
};
/**
@@ -490,6 +509,9 @@ void drm_mode_copy(struct drm_display_mode *dst,
const struct drm_display_mode *src);
struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
const struct drm_display_mode *mode);
bool drm_mode_match(const struct drm_display_mode *mode1,
const struct drm_display_mode *mode2,
unsigned int match_flags);
bool drm_mode_equal(const struct drm_display_mode *mode1,
const struct drm_display_mode *mode2);
bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1,
@@ -508,7 +530,7 @@ drm_mode_validate_ycbcr420(const struct drm_display_mode *mode,
void drm_mode_prune_invalid(struct drm_device *dev,
struct list_head *mode_list, bool verbose);
void drm_mode_sort(struct list_head *mode_list);
void drm_mode_connector_list_update(struct drm_connector *connector);
void drm_connector_list_update(struct drm_connector *connector);
/* parsing cmdline modes */
bool

17
include/drm/drm_modeset_helper_vtables.h
View File

@@ -785,7 +785,7 @@ struct drm_connector_helper_funcs {
*
* This function should fill in all modes currently valid for the sink
* into the &drm_connector.probed_modes list. It should also update the
* EDID property by calling drm_mode_connector_update_edid_property().
* EDID property by calling drm_connector_update_edid_property().
*
* The usual way to implement this is to cache the EDID retrieved in the
* probe callback somewhere in the driver-private connector structure.
@@ -974,6 +974,21 @@ struct drm_connector_helper_funcs {
*/
int (*atomic_check)(struct drm_connector *connector,
struct drm_connector_state *state);
/**
* @atomic_commit:
*
* This hook is to be used by drivers implementing writeback connectors
* that need a point when to commit the writeback job to the hardware.
* The writeback_job to commit is available in
* &drm_connector_state.writeback_job.
*
* This hook is optional.
*
* This callback is used by the atomic modeset helpers.
*/
void (*atomic_commit)(struct drm_connector *connector,
struct drm_connector_state *state);
};
/**

8
include/drm/drm_of.h
View File

@@ -17,6 +17,8 @@ struct drm_bridge;
struct device_node;
#ifdef CONFIG_OF
uint32_t drm_of_crtc_port_mask(struct drm_device *dev,
struct device_node *port);
uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
struct device_node *port);
void drm_of_component_match_add(struct device *master,
@@ -34,6 +36,12 @@ int drm_of_find_panel_or_bridge(const struct device_node *np,
struct drm_panel **panel,
struct drm_bridge **bridge);
#else
static inline uint32_t drm_of_crtc_port_mask(struct drm_device *dev,
struct device_node *port)
{
return 0;
}
static inline uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
struct device_node *port)
{

3
include/drm/drm_panel.h
View File

@@ -89,6 +89,7 @@ struct drm_panel {
struct drm_device *drm;
struct drm_connector *connector;
struct device *dev;
struct device_link *link;
const struct drm_panel_funcs *funcs;
@@ -199,7 +200,7 @@ struct drm_panel *of_drm_find_panel(const struct device_node *np);
#else
static inline struct drm_panel *of_drm_find_panel(const struct device_node *np)
{
return NULL;
return ERR_PTR(-ENODEV);
}
#endif

7
include/drm/drm_pci.h
View File

@@ -58,11 +58,4 @@ static inline int drm_get_pci_dev(struct pci_dev *pdev,
}
#endif
#define DRM_PCIE_SPEED_25 1
#define DRM_PCIE_SPEED_50 2
#define DRM_PCIE_SPEED_80 4
int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask);
int drm_pcie_get_max_link_width(struct drm_device *dev, u32 *mlw);
#endif /* _DRM_PCI_H_ */

197
include/drm/drm_plane.h
View File

@@ -34,31 +34,15 @@ struct drm_modeset_acquire_ctx;
/**
* struct drm_plane_state - mutable plane state
* @plane: backpointer to the plane
* @crtc_w: width of visible portion of plane on crtc
* @crtc_h: height of visible portion of plane on crtc
* @src_x: left position of visible portion of plane within
* plane (in 16.16)
* @src_y: upper position of visible portion of plane within
* plane (in 16.16)
* @src_w: width of visible portion of plane (in 16.16)
* @src_h: height of visible portion of plane (in 16.16)
* @alpha: opacity of the plane
* @rotation: rotation of the plane
* @zpos: priority of the given plane on crtc (optional)
* Note that multiple active planes on the same crtc can have an identical
* zpos value. The rule to solving the conflict is to compare the plane
* object IDs; the plane with a higher ID must be stacked on top of a
* plane with a lower ID.
* @normalized_zpos: normalized value of zpos: unique, range from 0 to N-1
* where N is the number of active planes for given crtc. Note that
* the driver must set drm_mode_config.normalize_zpos or call
* drm_atomic_normalize_zpos() to update this before it can be trusted.
* @src: clipped source coordinates of the plane (in 16.16)
* @dst: clipped destination coordinates of the plane
* @state: backpointer to global drm_atomic_state
*
* Please not that the destination coordinates @crtc_x, @crtc_y, @crtc_h and
* @crtc_w and the source coordinates @src_x, @src_y, @src_h and @src_w are the
* raw coordinates provided by userspace. Drivers should use
* drm_atomic_helper_check_plane_state() and only use the derived rectangles in
* @src and @dst to program the hardware.
*/
struct drm_plane_state {
/** @plane: backpointer to the plane */
struct drm_plane *plane;
/**
@@ -87,7 +71,7 @@ struct drm_plane_state {
* preserved.
*
* Drivers should store any implicit fence in this from their
* &drm_plane_helper.prepare_fb callback. See drm_gem_fb_prepare_fb()
* &drm_plane_helper_funcs.prepare_fb callback. See drm_gem_fb_prepare_fb()
* and drm_gem_fb_simple_display_pipe_prepare_fb() for suitable helpers.
*/
struct dma_fence *fence;
@@ -108,20 +92,60 @@ struct drm_plane_state {
*/
int32_t crtc_y;
/** @crtc_w: width of visible portion of plane on crtc */
/** @crtc_h: height of visible portion of plane on crtc */
uint32_t crtc_w, crtc_h;
/* Source values are 16.16 fixed point */
uint32_t src_x, src_y;
/**
* @src_x: left position of visible portion of plane within plane (in
* 16.16 fixed point).
*/
uint32_t src_x;
/**
* @src_y: upper position of visible portion of plane within plane (in
* 16.16 fixed point).
*/
uint32_t src_y;
/** @src_w: width of visible portion of plane (in 16.16) */
/** @src_h: height of visible portion of plane (in 16.16) */
uint32_t src_h, src_w;
/* Plane opacity */
/**
* @alpha:
* Opacity of the plane with 0 as completely transparent and 0xffff as
* completely opaque. See drm_plane_create_alpha_property() for more
* details.
*/
u16 alpha;
/* Plane rotation */
/**
* @rotation:
* Rotation of the plane. See drm_plane_create_rotation_property() for
* more details.
*/
unsigned int rotation;
/* Plane zpos */
/**
* @zpos:
* Priority of the given plane on crtc (optional).
*
* Note that multiple active planes on the same crtc can have an
* identical zpos value. The rule to solving the conflict is to compare
* the plane object IDs; the plane with a higher ID must be stacked on
* top of a plane with a lower ID.
*
* See drm_plane_create_zpos_property() and
* drm_plane_create_zpos_immutable_property() for more details.
*/
unsigned int zpos;
/**
* @normalized_zpos:
* Normalized value of zpos: unique, range from 0 to N-1 where N is the
* number of active planes for given crtc. Note that the driver must set
* &drm_mode_config.normalize_zpos or call drm_atomic_normalize_zpos() to
* update this before it can be trusted.
*/
unsigned int normalized_zpos;
/**
@@ -138,7 +162,8 @@ struct drm_plane_state {
*/
enum drm_color_range color_range;
/* Clipped coordinates */
/** @src: clipped source coordinates of the plane (in 16.16) */
/** @dst: clipped destination coordinates of the plane */
struct drm_rect src, dst;
/**
@@ -157,6 +182,7 @@ struct drm_plane_state {
*/
struct drm_crtc_commit *commit;
/** @state: backpointer to global drm_atomic_state */
struct drm_atomic_state *state;
};
@@ -288,6 +314,8 @@ struct drm_plane_funcs {
* cleaned up by calling the @atomic_destroy_state hook in this
* structure.
*
* This callback is mandatory for atomic drivers.
*
* Atomic drivers which don't subclass &struct drm_plane_state should use
* drm_atomic_helper_plane_duplicate_state(). Drivers that subclass the
* state structure to extend it with driver-private state should use
@@ -314,6 +342,8 @@ struct drm_plane_funcs {
*
* Destroy a state duplicated with @atomic_duplicate_state and release
* or unreference all resources it references
*
* This callback is mandatory for atomic drivers.
*/
void (*atomic_destroy_state)(struct drm_plane *plane,
struct drm_plane_state *state);
@@ -431,7 +461,10 @@ struct drm_plane_funcs {
* This optional hook is used for the DRM to determine if the given
* format/modifier combination is valid for the plane. This allows the
* DRM to generate the correct format bitmask (which formats apply to
* which modifier).
* which modifier), and to valdiate modifiers at atomic_check time.
*
* If not present, then any modifier in the plane's modifier
* list is allowed with any of the plane's formats.
*
* Returns:
*
@@ -492,30 +525,27 @@ enum drm_plane_type {
/**
* struct drm_plane - central DRM plane control structure
* @dev: DRM device this plane belongs to
* @head: for list management
* @name: human readable name, can be overwritten by the driver
* @base: base mode object
* @possible_crtcs: pipes this plane can be bound to
* @format_types: array of formats supported by this plane
* @format_count: number of formats supported
* @format_default: driver hasn't supplied supported formats for the plane
* @modifiers: array of modifiers supported by this plane
* @modifier_count: number of modifiers supported
* @old_fb: Temporary tracking of the old fb while a modeset is ongoing. Used by
* drm_mode_set_config_internal() to implement correct refcounting.
* @funcs: helper functions
* @properties: property tracking for this plane
* @type: type of plane (overlay, primary, cursor)
* @alpha_property: alpha property for this plane
* @zpos_property: zpos property for this plane
* @rotation_property: rotation property for this plane
* @helper_private: mid-layer private data
*
* Planes represent the scanout hardware of a display block. They receive their
* input data from a &drm_framebuffer and feed it to a &drm_crtc. Planes control
* the color conversion, see `Plane Composition Properties`_ for more details,
* and are also involved in the color conversion of input pixels, see `Color
* Management Properties`_ for details on that.
*/
struct drm_plane {
/** @dev: DRM device this plane belongs to */
struct drm_device *dev;
/**
* @head:
*
* List of all planes on @dev, linked from &drm_mode_config.plane_list.
* Invariant over the lifetime of @dev and therefore does not need
* locking.
*/
struct list_head head;
/** @name: human readable name, can be overwritten by the driver */
char *name;
/**
@@ -529,35 +559,62 @@ struct drm_plane {
*/
struct drm_modeset_lock mutex;
/** @base: base mode object */
struct drm_mode_object base;
/**
* @possible_crtcs: pipes this plane can be bound to constructed from
* drm_crtc_mask()
*/
uint32_t possible_crtcs;
/** @format_types: array of formats supported by this plane */
uint32_t *format_types;
/** @format_count: Size of the array pointed at by @format_types. */
unsigned int format_count;
/**
* @format_default: driver hasn't supplied supported formats for the
* plane. Used by the drm_plane_init compatibility wrapper only.
*/
bool format_default;
/** @modifiers: array of modifiers supported by this plane */
uint64_t *modifiers;
/** @modifier_count: Size of the array pointed at by @modifier_count. */
unsigned int modifier_count;
/**
* @crtc: Currently bound CRTC, only really meaningful for non-atomic
* drivers. Atomic drivers should instead check &drm_plane_state.crtc.
* @crtc:
*
* Currently bound CRTC, only meaningful for non-atomic drivers. For
* atomic drivers this is forced to be NULL, atomic drivers should
* instead check &drm_plane_state.crtc.
*/
struct drm_crtc *crtc;
/**
* @fb: Currently bound framebuffer, only really meaningful for
* non-atomic drivers. Atomic drivers should instead check
* &drm_plane_state.fb.
* @fb:
*
* Currently bound framebuffer, only meaningful for non-atomic drivers.
* For atomic drivers this is forced to be NULL, atomic drivers should
* instead check &drm_plane_state.fb.
*/
struct drm_framebuffer *fb;
/**
* @old_fb:
*
* Temporary tracking of the old fb while a modeset is ongoing. Only
* used by non-atomic drivers, forced to be NULL for atomic drivers.
*/
struct drm_framebuffer *old_fb;
/** @funcs: plane control functions */
const struct drm_plane_funcs *funcs;
/** @properties: property tracking for this plane */
struct drm_object_properties properties;
/** @type: Type of plane, see &enum drm_plane_type for details. */
enum drm_plane_type type;
/**
@@ -566,6 +623,7 @@ struct drm_plane {
*/
unsigned index;
/** @helper_private: mid-layer private data */
const struct drm_plane_helper_funcs *helper_private;
/**
@@ -583,8 +641,23 @@ struct drm_plane {
*/
struct drm_plane_state *state;
/**
* @alpha_property:
* Optional alpha property for this plane. See
* drm_plane_create_alpha_property().
*/
struct drm_property *alpha_property;
/**
* @zpos_property:
* Optional zpos property for this plane. See
* drm_plane_create_zpos_property().
*/
struct drm_property *zpos_property;
/**
* @rotation_property:
* Optional rotation property for this plane. See
* drm_plane_create_rotation_property().
*/
struct drm_property *rotation_property;
/**
@@ -632,10 +705,20 @@ void drm_plane_cleanup(struct drm_plane *plane);
* Given a registered plane, return the index of that plane within a DRM
* device's list of planes.
*/
static inline unsigned int drm_plane_index(struct drm_plane *plane)
static inline unsigned int drm_plane_index(const struct drm_plane *plane)
{
return plane->index;
}
/**
* drm_plane_mask - find the mask of a registered plane
* @plane: plane to find mask for
*/
static inline u32 drm_plane_mask(const struct drm_plane *plane)
{
return 1 << drm_plane_index(plane);
}
struct drm_plane * drm_plane_from_index(struct drm_device *dev, int idx);
void drm_plane_force_disable(struct drm_plane *plane);
@@ -671,7 +754,7 @@ static inline struct drm_plane *drm_plane_find(struct drm_device *dev,
*/
#define drm_for_each_plane_mask(plane, dev, plane_mask) \
list_for_each_entry((plane), &(dev)->mode_config.plane_list, head) \
for_each_if ((plane_mask) & (1 << drm_plane_index(plane)))
for_each_if ((plane_mask) & drm_plane_mask(plane))
/**
* drm_for_each_legacy_plane - iterate over all planes for legacy userspace

6
include/drm/drm_plane_helper.h
View File

@@ -67,8 +67,10 @@ int drm_plane_helper_update(struct drm_plane *plane, struct drm_crtc *crtc,
int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h);
int drm_plane_helper_disable(struct drm_plane *plane);
uint32_t src_w, uint32_t src_h,
struct drm_modeset_acquire_ctx *ctx);
int drm_plane_helper_disable(struct drm_plane *plane,
struct drm_modeset_acquire_ctx *ctx);
/* For use by drm_crtc_helper.c */
int drm_plane_helper_commit(struct drm_plane *plane,

6
include/drm/drm_prime.h
View File

@@ -82,7 +82,7 @@ int drm_gem_prime_fd_to_handle(struct drm_device *dev,
struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
struct dma_buf_export_info *exp_info);
void drm_gem_dmabuf_release(struct dma_buf *dma_buf);
int drm_gem_map_attach(struct dma_buf *dma_buf, struct device *target_dev,
int drm_gem_map_attach(struct dma_buf *dma_buf,
struct dma_buf_attachment *attach);
void drm_gem_map_detach(struct dma_buf *dma_buf,
struct dma_buf_attachment *attach);
@@ -93,10 +93,6 @@ void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
enum dma_data_direction dir);
void *drm_gem_dmabuf_vmap(struct dma_buf *dma_buf);
void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, void *vaddr);
void *drm_gem_dmabuf_kmap_atomic(struct dma_buf *dma_buf,
unsigned long page_num);
void drm_gem_dmabuf_kunmap_atomic(struct dma_buf *dma_buf,
unsigned long page_num, void *addr);
void *drm_gem_dmabuf_kmap(struct dma_buf *dma_buf, unsigned long page_num);
void drm_gem_dmabuf_kunmap(struct dma_buf *dma_buf, unsigned long page_num,
void *addr);

6
include/drm/drm_print.h
View File

@@ -195,6 +195,7 @@ static inline struct drm_printer drm_debug_printer(const char *prefix)
#define DRM_UT_VBL 0x20
#define DRM_UT_STATE 0x40
#define DRM_UT_LEASE 0x80
#define DRM_UT_DP 0x100
__printf(3, 4)
void drm_dev_printk(const struct device *dev, const char *level,
@@ -307,6 +308,11 @@ void drm_err(const char *format, ...);
#define DRM_DEBUG_LEASE(fmt, ...) \
drm_dbg(DRM_UT_LEASE, fmt, ##__VA_ARGS__)
#define DRM_DEV_DEBUG_DP(dev, fmt, ...) \
drm_dev_dbg(dev, DRM_UT_DP, fmt, ## __VA_ARGS__)
#define DRM_DEBUG_DP(dev, fmt, ...) \
drm_dbg(DRM_UT_DP, fmt, ## __VA_ARGS__)
#define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, category, fmt, ...) \
({ \
static DEFINE_RATELIMIT_STATE(_rs, \

6
include/drm/drm_property.h
View File

@@ -147,10 +147,10 @@ struct drm_property {
* properties are not exposed to legacy userspace.
*
* DRM_MODE_PROP_IMMUTABLE
* Set for properties where userspace cannot be changed by
* Set for properties whose values cannot be changed by
* userspace. The kernel is allowed to update the value of these
* properties. This is generally used to expose probe state to
* usersapce, e.g. the EDID, or the connector path property on DP
* userspace, e.g. the EDID, or the connector path property on DP
* MST sinks.
*/
uint32_t flags;
@@ -260,7 +260,7 @@ struct drm_property *drm_property_create_object(struct drm_device *dev,
uint32_t type);
struct drm_property *drm_property_create_bool(struct drm_device *dev,
u32 flags, const char *name);
int drm_property_add_enum(struct drm_property *property, int index,
int drm_property_add_enum(struct drm_property *property,
uint64_t value, const char *name);
void drm_property_destroy(struct drm_device *dev, struct drm_property *property);

3
include/drm/drm_rect.h
View File

@@ -175,8 +175,7 @@ static inline bool drm_rect_equals(const struct drm_rect *r1,
bool drm_rect_intersect(struct drm_rect *r, const struct drm_rect *clip);
bool drm_rect_clip_scaled(struct drm_rect *src, struct drm_rect *dst,
const struct drm_rect *clip,
int hscale, int vscale);
const struct drm_rect *clip);
int drm_rect_calc_hscale(const struct drm_rect *src,
const struct drm_rect *dst,
int min_hscale, int max_hscale);

136
include/drm/drm_writeback.h Normal file
View File

@@ -0,0 +1,136 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
* Author: Brian Starkey <brian.starkey@arm.com>
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU licence.
*/
#ifndef __DRM_WRITEBACK_H__
#define __DRM_WRITEBACK_H__
#include <drm/drm_connector.h>
#include <drm/drm_encoder.h>
#include <linux/workqueue.h>
struct drm_writeback_connector {
struct drm_connector base;
/**
* @encoder: Internal encoder used by the connector to fulfill
* the DRM framework requirements. The users of the
* @drm_writeback_connector control the behaviour of the @encoder
* by passing the @enc_funcs parameter to drm_writeback_connector_init()
* function.
*/
struct drm_encoder encoder;
/**
* @pixel_formats_blob_ptr:
*
* DRM blob property data for the pixel formats list on writeback
* connectors
* See also drm_writeback_connector_init()
*/
struct drm_property_blob *pixel_formats_blob_ptr;
/** @job_lock: Protects job_queue */
spinlock_t job_lock;
/**
* @job_queue:
*
* Holds a list of a connector's writeback jobs; the last item is the
* most recent. The first item may be either waiting for the hardware
* to begin writing, or currently being written.
*
* See also: drm_writeback_queue_job() and
* drm_writeback_signal_completion()
*/
struct list_head job_queue;
/**
* @fence_context:
*
* timeline context used for fence operations.
*/
unsigned int fence_context;
/**
* @fence_lock:
*
* spinlock to protect the fences in the fence_context.
*/
spinlock_t fence_lock;
/**
* @fence_seqno:
*
* Seqno variable used as monotonic counter for the fences
* created on the connector's timeline.
*/
unsigned long fence_seqno;
/**
* @timeline_name:
*
* The name of the connector's fence timeline.
*/
char timeline_name[32];
};
struct drm_writeback_job {
/**
* @cleanup_work:
*
* Used to allow drm_writeback_signal_completion to defer dropping the
* framebuffer reference to a workqueue
*/
struct work_struct cleanup_work;
/**
* @list_entry:
*
* List item for the writeback connector's @job_queue
*/
struct list_head list_entry;
/**
* @fb:
*
* Framebuffer to be written to by the writeback connector. Do not set
* directly, use drm_atomic_set_writeback_fb_for_connector()
*/
struct drm_framebuffer *fb;
/**
* @out_fence:
*
* Fence which will signal once the writeback has completed
*/
struct dma_fence *out_fence;
};
static inline struct drm_writeback_connector *
drm_connector_to_writeback(struct drm_connector *connector)
{
return container_of(connector, struct drm_writeback_connector, base);
}
int drm_writeback_connector_init(struct drm_device *dev,
struct drm_writeback_connector *wb_connector,
const struct drm_connector_funcs *con_funcs,
const struct drm_encoder_helper_funcs *enc_helper_funcs,
const u32 *formats, int n_formats);
void drm_writeback_queue_job(struct drm_writeback_connector *wb_connector,
struct drm_writeback_job *job);
void drm_writeback_cleanup_job(struct drm_writeback_job *job);
void
drm_writeback_signal_completion(struct drm_writeback_connector *wb_connector,
int status);
struct dma_fence *
drm_writeback_get_out_fence(struct drm_writeback_connector *wb_connector);
#endif

174
include/drm/gpu_scheduler.h
View File

@@ -27,6 +27,8 @@
#include <drm/spsc_queue.h>
#include <linux/dma-fence.h>
#define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
struct drm_gpu_scheduler;
struct drm_sched_rq;
@@ -43,18 +45,39 @@ enum drm_sched_priority {
};
/**
* A scheduler entity is a wrapper around a job queue or a group
* of other entities. Entities take turns emitting jobs from their
* job queues to corresponding hardware ring based on scheduling
* policy.
*/
* struct drm_sched_entity - A wrapper around a job queue (typically
* attached to the DRM file_priv).
*
* @list: used to append this struct to the list of entities in the
* runqueue.
* @rq: runqueue to which this entity belongs.
* @rq_lock: lock to modify the runqueue to which this entity belongs.
* @sched: the scheduler instance to which this entity is enqueued.
* @job_queue: the list of jobs of this entity.
* @fence_seq: a linearly increasing seqno incremented with each
* new &drm_sched_fence which is part of the entity.
* @fence_context: a unique context for all the fences which belong
* to this entity.
* The &drm_sched_fence.scheduled uses the
* fence_context but &drm_sched_fence.finished uses
* fence_context + 1.
* @dependency: the dependency fence of the job which is on the top
* of the job queue.
* @cb: callback for the dependency fence above.
* @guilty: points to ctx's guilty.
* @fini_status: contains the exit status in case the process was signalled.
* @last_scheduled: points to the finished fence of the last scheduled job.
*
* Entities will emit jobs in order to their corresponding hardware
* ring, and the scheduler will alternate between entities based on
* scheduling policy.
*/
struct drm_sched_entity {
struct list_head list;
struct drm_sched_rq *rq;
spinlock_t rq_lock;
struct drm_gpu_scheduler *sched;
spinlock_t queue_lock;
struct spsc_queue job_queue;
atomic_t fence_seq;
@@ -62,32 +85,102 @@ struct drm_sched_entity {
struct dma_fence *dependency;
struct dma_fence_cb cb;
atomic_t *guilty; /* points to ctx's guilty */
atomic_t *guilty;
struct dma_fence *last_scheduled;
};
/**
* struct drm_sched_rq - queue of entities to be scheduled.
*
* @lock: to modify the entities list.
* @sched: the scheduler to which this rq belongs to.
* @entities: list of the entities to be scheduled.
* @current_entity: the entity which is to be scheduled.
*
* Run queue is a set of entities scheduling command submissions for
* one specific ring. It implements the scheduling policy that selects
* the next entity to emit commands from.
*/
*/
struct drm_sched_rq {
spinlock_t lock;
struct drm_gpu_scheduler *sched;
struct list_head entities;
struct drm_sched_entity *current_entity;
};
/**
* struct drm_sched_fence - fences corresponding to the scheduling of a job.
*/
struct drm_sched_fence {
/**
* @scheduled: this fence is what will be signaled by the scheduler
* when the job is scheduled.
*/
struct dma_fence scheduled;
/**
* @finished: this fence is what will be signaled by the scheduler
* when the job is completed.
*
* When setting up an out fence for the job, you should use
* this, since it's available immediately upon
* drm_sched_job_init(), and the fence returned by the driver
* from run_job() won't be created until the dependencies have
* resolved.
*/
struct dma_fence finished;
/**
* @cb: the callback for the parent fence below.
*/
struct dma_fence_cb cb;
/**
* @parent: the fence returned by &drm_sched_backend_ops.run_job
* when scheduling the job on hardware. We signal the
* &drm_sched_fence.finished fence once parent is signalled.
*/
struct dma_fence *parent;
/**
* @sched: the scheduler instance to which the job having this struct
* belongs to.
*/
struct drm_gpu_scheduler *sched;
/**
* @lock: the lock used by the scheduled and the finished fences.
*/
spinlock_t lock;
/**
* @owner: job owner for debugging
*/
void *owner;
};
struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f);
/**
* struct drm_sched_job - A job to be run by an entity.
*
* @queue_node: used to append this struct to the queue of jobs in an entity.
* @sched: the scheduler instance on which this job is scheduled.
* @s_fence: contains the fences for the scheduling of job.
* @finish_cb: the callback for the finished fence.
* @finish_work: schedules the function @drm_sched_job_finish once the job has
* finished to remove the job from the
* @drm_gpu_scheduler.ring_mirror_list.
* @node: used to append this struct to the @drm_gpu_scheduler.ring_mirror_list.
* @work_tdr: schedules a delayed call to @drm_sched_job_timedout after the timeout
* interval is over.
* @id: a unique id assigned to each job scheduled on the scheduler.
* @karma: increment on every hang caused by this job. If this exceeds the hang
* limit of the scheduler then the job is marked guilty and will not
* be scheduled further.
* @s_priority: the priority of the job.
* @entity: the entity to which this job belongs.
*
* A job is created by the driver using drm_sched_job_init(), and
* should call drm_sched_entity_push_job() once it wants the scheduler
* to schedule the job.
*/
struct drm_sched_job {
struct spsc_node queue_node;
struct drm_gpu_scheduler *sched;
@@ -99,6 +192,7 @@ struct drm_sched_job {
uint64_t id;
atomic_t karma;
enum drm_sched_priority s_priority;
struct drm_sched_entity *entity;
};
static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job,
@@ -108,20 +202,64 @@ static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job,
}
/**
* struct drm_sched_backend_ops
*
* Define the backend operations called by the scheduler,
* these functions should be implemented in driver side
*/
* these functions should be implemented in driver side.
*/
struct drm_sched_backend_ops {
/**
* @dependency: Called when the scheduler is considering scheduling
* this job next, to get another struct dma_fence for this job to
* block on. Once it returns NULL, run_job() may be called.
*/
struct dma_fence *(*dependency)(struct drm_sched_job *sched_job,
struct drm_sched_entity *s_entity);
/**
* @run_job: Called to execute the job once all of the dependencies
* have been resolved. This may be called multiple times, if
* timedout_job() has happened and drm_sched_job_recovery()
* decides to try it again.
*/
struct dma_fence *(*run_job)(struct drm_sched_job *sched_job);
/**
* @timedout_job: Called when a job has taken too long to execute,
* to trigger GPU recovery.
*/
void (*timedout_job)(struct drm_sched_job *sched_job);
/**
* @free_job: Called once the job's finished fence has been signaled
* and it's time to clean it up.
*/
void (*free_job)(struct drm_sched_job *sched_job);
};
/**
* One scheduler is implemented for each hardware ring
*/
* struct drm_gpu_scheduler
*
* @ops: backend operations provided by the driver.
* @hw_submission_limit: the max size of the hardware queue.
* @timeout: the time after which a job is removed from the scheduler.
* @name: name of the ring for which this scheduler is being used.
* @sched_rq: priority wise array of run queues.
* @wake_up_worker: the wait queue on which the scheduler sleeps until a job
* is ready to be scheduled.
* @job_scheduled: once @drm_sched_entity_do_release is called the scheduler
* waits on this wait queue until all the scheduled jobs are
* finished.
* @hw_rq_count: the number of jobs currently in the hardware queue.
* @job_id_count: used to assign unique id to the each job.
* @thread: the kthread on which the scheduler which run.
* @ring_mirror_list: the list of jobs which are currently in the job queue.
* @job_list_lock: lock to protect the ring_mirror_list.
* @hang_limit: once the hangs by a job crosses this limit then it is marked
* guilty and it will be considered for scheduling further.
*
* One scheduler is implemented for each hardware ring.
*/
struct drm_gpu_scheduler {
const struct drm_sched_backend_ops *ops;
uint32_t hw_submission_limit;
@@ -144,12 +282,16 @@ int drm_sched_init(struct drm_gpu_scheduler *sched,
const char *name);
void drm_sched_fini(struct drm_gpu_scheduler *sched);
int drm_sched_entity_init(struct drm_gpu_scheduler *sched,
struct drm_sched_entity *entity,
struct drm_sched_rq *rq,
uint32_t jobs, atomic_t *guilty);
int drm_sched_entity_init(struct drm_sched_entity *entity,
struct drm_sched_rq **rq_list,
unsigned int num_rq_list,
atomic_t *guilty);
long drm_sched_entity_flush(struct drm_gpu_scheduler *sched,
struct drm_sched_entity *entity, long timeout);
void drm_sched_entity_fini(struct drm_gpu_scheduler *sched,
struct drm_sched_entity *entity);
void drm_sched_entity_destroy(struct drm_gpu_scheduler *sched,
struct drm_sched_entity *entity);
void drm_sched_entity_push_job(struct drm_sched_job *sched_job,
struct drm_sched_entity *entity);
void drm_sched_entity_set_rq(struct drm_sched_entity *entity,

82
include/drm/gpu_scheduler_trace.h
View File

@@ -1,82 +0,0 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#if !defined(_GPU_SCHED_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
#define _GPU_SCHED_TRACE_H_
#include <linux/stringify.h>
#include <linux/types.h>
#include <linux/tracepoint.h>
#include <drm/drmP.h>
#undef TRACE_SYSTEM
#define TRACE_SYSTEM gpu_scheduler
#define TRACE_INCLUDE_FILE gpu_scheduler_trace
TRACE_EVENT(drm_sched_job,
TP_PROTO(struct drm_sched_job *sched_job, struct drm_sched_entity *entity),
TP_ARGS(sched_job, entity),
TP_STRUCT__entry(
__field(struct drm_sched_entity *, entity)
__field(struct dma_fence *, fence)
__field(const char *, name)
__field(uint64_t, id)
__field(u32, job_count)
__field(int, hw_job_count)
),
TP_fast_assign(
__entry->entity = entity;
__entry->id = sched_job->id;
__entry->fence = &sched_job->s_fence->finished;
__entry->name = sched_job->sched->name;
__entry->job_count = spsc_queue_count(&entity->job_queue);
__entry->hw_job_count = atomic_read(
&sched_job->sched->hw_rq_count);
),
TP_printk("entity=%p, id=%llu, fence=%p, ring=%s, job count:%u, hw job count:%d",
__entry->entity, __entry->id,
__entry->fence, __entry->name,
__entry->job_count, __entry->hw_job_count)
);
TRACE_EVENT(drm_sched_process_job,
TP_PROTO(struct drm_sched_fence *fence),
TP_ARGS(fence),
TP_STRUCT__entry(
__field(struct dma_fence *, fence)
),
TP_fast_assign(
__entry->fence = &fence->finished;
),
TP_printk("fence=%p signaled", __entry->fence)
);
#endif
/* This part must be outside protection */
#undef TRACE_INCLUDE_PATH
#define TRACE_INCLUDE_PATH .
#include <trace/define_trace.h>

23
include/drm/tinydrm/tinydrm.h
View File

@@ -16,16 +16,31 @@
/**
* struct tinydrm_device - tinydrm device
* @drm: DRM device
* @pipe: Display pipe structure
* @dirty_lock: Serializes framebuffer flushing
* @fb_funcs: Framebuffer functions used when creating framebuffers
*/
struct tinydrm_device {
/**
* @drm: DRM device
*/
struct drm_device *drm;
/**
* @pipe: Display pipe structure
*/
struct drm_simple_display_pipe pipe;
/**
* @dirty_lock: Serializes framebuffer flushing
*/
struct mutex dirty_lock;
/**
* @fb_funcs: Framebuffer functions used when creating framebuffers
*/
const struct drm_framebuffer_funcs *fb_funcs;
/**
* @fb_dirty: Framebuffer dirty callback
*/
int (*fb_dirty)(struct drm_framebuffer *framebuffer,
struct drm_file *file_priv, unsigned flags,
unsigned color, struct drm_clip_rect *clips,

25
include/drm/ttm/ttm_bo_api.h
View File

@@ -283,18 +283,30 @@ struct ttm_operation_ctx {
/* when serving page fault or suspend, allow alloc anyway */
#define TTM_OPT_FLAG_FORCE_ALLOC 0x2
/**
* ttm_bo_get - reference a struct ttm_buffer_object
*
* @bo: The buffer object.
*/
static inline void ttm_bo_get(struct ttm_buffer_object *bo)
{
kref_get(&bo->kref);
}
/**
* ttm_bo_reference - reference a struct ttm_buffer_object
*
* @bo: The buffer object.
*
* Returns a refcounted pointer to a buffer object.
*
* This function is deprecated. Use @ttm_bo_get instead.
*/
static inline struct ttm_buffer_object *
ttm_bo_reference(struct ttm_buffer_object *bo)
{
kref_get(&bo->kref);
ttm_bo_get(bo);
return bo;
}
@@ -345,12 +357,23 @@ int ttm_bo_validate(struct ttm_buffer_object *bo,
struct ttm_placement *placement,
struct ttm_operation_ctx *ctx);
/**
* ttm_bo_put
*
* @bo: The buffer object.
*
* Unreference a buffer object.
*/
void ttm_bo_put(struct ttm_buffer_object *bo);
/**
* ttm_bo_unref
*
* @bo: The buffer object.
*
* Unreference and clear a pointer to a buffer object.
*
* This function is deprecated. Use @ttm_bo_put instead.
*/
void ttm_bo_unref(struct ttm_buffer_object **bo);

129
include/dt-bindings/clock/actions,s900-cmu.h Normal file
View File

@@ -0,0 +1,129 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Device Tree binding constants for Actions Semi S900 Clock Management Unit
//
// Copyright (c) 2014 Actions Semi Inc.
// Copyright (c) 2018 Linaro Ltd.
#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
#define __DT_BINDINGS_CLOCK_S900_CMU_H
#define CLK_NONE 0
/* fixed rate clocks */
#define CLK_LOSC 1
#define CLK_HOSC 2
/* pll clocks */
#define CLK_CORE_PLL 3
#define CLK_DEV_PLL 4
#define CLK_DDR_PLL 5
#define CLK_NAND_PLL 6
#define CLK_DISPLAY_PLL 7
#define CLK_DSI_PLL 8
#define CLK_ASSIST_PLL 9
#define CLK_AUDIO_PLL 10
/* system clock */
#define CLK_CPU 15
#define CLK_DEV 16
#define CLK_NOC 17
#define CLK_NOC_MUX 18
#define CLK_NOC_DIV 19
#define CLK_AHB 20
#define CLK_APB 21
#define CLK_DMAC 22
/* peripheral device clock */
#define CLK_GPIO 23
#define CLK_BISP 24
#define CLK_CSI0 25
#define CLK_CSI1 26
#define CLK_DE0 27
#define CLK_DE1 28
#define CLK_DE2 29
#define CLK_DE3 30
#define CLK_DSI 32
#define CLK_GPU 33
#define CLK_GPU_CORE 34
#define CLK_GPU_MEM 35
#define CLK_GPU_SYS 36
#define CLK_HDE 37
#define CLK_I2C0 38
#define CLK_I2C1 39
#define CLK_I2C2 40
#define CLK_I2C3 41
#define CLK_I2C4 42
#define CLK_I2C5 43
#define CLK_I2SRX 44
#define CLK_I2STX 45
#define CLK_IMX 46
#define CLK_LCD 47
#define CLK_NAND0 48
#define CLK_NAND1 49
#define CLK_PWM0 50
#define CLK_PWM1 51
#define CLK_PWM2 52
#define CLK_PWM3 53
#define CLK_PWM4 54
#define CLK_PWM5 55
#define CLK_SD0 56
#define CLK_SD1 57
#define CLK_SD2 58
#define CLK_SD3 59
#define CLK_SENSOR 60
#define CLK_SPEED_SENSOR 61
#define CLK_SPI0 62
#define CLK_SPI1 63
#define CLK_SPI2 64
#define CLK_SPI3 65
#define CLK_THERMAL_SENSOR 66
#define CLK_UART0 67
#define CLK_UART1 68
#define CLK_UART2 69
#define CLK_UART3 70
#define CLK_UART4 71
#define CLK_UART5 72
#define CLK_UART6 73
#define CLK_VCE 74
#define CLK_VDE 75
#define CLK_USB3_480MPLL0 76
#define CLK_USB3_480MPHY0 77
#define CLK_USB3_5GPHY 78
#define CLK_USB3_CCE 79
#define CLK_USB3_MAC 80
#define CLK_TIMER 83
#define CLK_HDMI_AUDIO 84
#define CLK_24M 85
#define CLK_EDP 86
#define CLK_24M_EDP 87
#define CLK_EDP_PLL 88
#define CLK_EDP_LINK 89
#define CLK_USB2H0_PLLEN 90
#define CLK_USB2H0_PHY 91
#define CLK_USB2H0_CCE 92
#define CLK_USB2H1_PLLEN 93
#define CLK_USB2H1_PHY 94
#define CLK_USB2H1_CCE 95
#define CLK_DDR0 96
#define CLK_DDR1 97
#define CLK_DMM 98
#define CLK_ETH_MAC 99
#define CLK_RMII_REF 100
#define CLK_NR_CLKS (CLK_RMII_REF + 1)
#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */

4
include/dt-bindings/clock/aspeed-clock.h
View File

@@ -38,6 +38,7 @@
#define ASPEED_CLK_MAC 32
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
#define ASPEED_CLK_24M 35
#define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1
@@ -45,8 +46,9 @@
#define ASPEED_RESET_JTAG_MASTER 3
#define ASPEED_RESET_MIC 4
#define ASPEED_RESET_PWM 5
#define ASPEED_RESET_PCIVGA 6
#define ASPEED_RESET_PECI 6
#define ASPEED_RESET_I2C 7
#define ASPEED_RESET_AHB 8
#define ASPEED_RESET_CRT1 9
#endif

26
include/dt-bindings/clock/axg-aoclkc.h Normal file
View File

@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
*/
#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
#define CLKID_AO_REMOTE 0
#define CLKID_AO_I2C_MASTER 1
#define CLKID_AO_I2C_SLAVE 2
#define CLKID_AO_UART1 3
#define CLKID_AO_UART2 4
#define CLKID_AO_IR_BLASTER 5
#define CLKID_AO_SAR_ADC 6
#define CLKID_AO_CLK81 7
#define CLKID_AO_SAR_ADC_SEL 8
#define CLKID_AO_SAR_ADC_DIV 9
#define CLKID_AO_SAR_ADC_CLK 10
#define CLKID_AO_ALT_XTAL 11
#endif

24
include/dt-bindings/clock/bcm-sr.h
View File

@@ -35,7 +35,7 @@
/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
#define BCM_SR_GENPLL0 0
#define BCM_SR_GENPLL0_SATA_CLK 1
#define BCM_SR_GENPLL0_125M_CLK 1
#define BCM_SR_GENPLL0_SCR_CLK 2
#define BCM_SR_GENPLL0_250M_CLK 3
#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
@@ -50,9 +50,11 @@
/* GENPLL 2 clock channel ID NITRO MHB*/
#define BCM_SR_GENPLL2 0
#define BCM_SR_GENPLL2_NIC_CLK 1
#define BCM_SR_GENPLL2_250_NITRO_CLK 2
#define BCM_SR_GENPLL2_TS_500_CLK 2
#define BCM_SR_GENPLL2_125_NITRO_CLK 3
#define BCM_SR_GENPLL2_CHIMP_CLK 4
#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5
#define BCM_SR_GENPLL2_FS4_CLK 6
/* GENPLL 3 HSLS clock channel ID */
#define BCM_SR_GENPLL3 0
@@ -62,11 +64,16 @@
/* GENPLL 4 SCR clock channel ID */
#define BCM_SR_GENPLL4 0
#define BCM_SR_GENPLL4_CCN_CLK 1
#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
#define BCM_SR_GENPLL4_NOC_CLK 3
#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4
#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
/* GENPLL 5 FS4 clock channel ID */
#define BCM_SR_GENPLL5 0
#define BCM_SR_GENPLL5_FS_CLK 1
#define BCM_SR_GENPLL5_SPU_CLK 2
#define BCM_SR_GENPLL5_FS4_HF_CLK 1
#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2
#define BCM_SR_GENPLL5_RAID_AE_CLK 3
/* GENPLL 6 NITRO clock channel ID */
#define BCM_SR_GENPLL6 0
@@ -74,13 +81,16 @@
/* LCPLL0 clock channel ID */
#define BCM_SR_LCPLL0 0
#define BCM_SR_LCPLL0_SATA_REF_CLK 1
#define BCM_SR_LCPLL0_USB_REF_CLK 2
#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
#define BCM_SR_LCPLL0_SATA_REFP_CLK 1
#define BCM_SR_LCPLL0_SATA_REFN_CLK 2
#define BCM_SR_LCPLL0_SATA_350_CLK 3
#define BCM_SR_LCPLL0_SATA_500_CLK 4
/* LCPLL1 clock channel ID */
#define BCM_SR_LCPLL1 0
#define BCM_SR_LCPLL1_WAN_CLK 1
#define BCM_SR_LCPLL1_USB_REF_CLK 2
#define BCM_SR_LCPLL1_CRMU_TS_CLK 3
/* LCPLL PCIE clock channel ID */
#define BCM_SR_LCPLL_PCIE 0

2
include/dt-bindings/clock/gxbb-clkc.h
View File

@@ -125,5 +125,7 @@
#define CLKID_VAPB_1 138
#define CLKID_VAPB_SEL 139
#define CLKID_VAPB 140
#define CLKID_VDEC_1 153
#define CLKID_VDEC_HEVC 156
#endif /* __GXBB_CLKC_H */

8
include/dt-bindings/clock/histb-clock.h
View File

@@ -62,6 +62,14 @@
#define HISTB_USB2_PHY1_REF_CLK 40
#define HISTB_USB2_PHY2_REF_CLK 41
#define HISTB_COMBPHY0_CLK 42
#define HISTB_USB3_BUS_CLK 43
#define HISTB_USB3_UTMI_CLK 44
#define HISTB_USB3_PIPE_CLK 45
#define HISTB_USB3_SUSPEND_CLK 46
#define HISTB_USB3_BUS_CLK1 47
#define HISTB_USB3_UTMI_CLK1 48
#define HISTB_USB3_PIPE_CLK1 49
#define HISTB_USB3_SUSPEND_CLK1 50
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1

4
include/dt-bindings/clock/imx6qdl-clock.h
View File

@@ -271,6 +271,8 @@
#define IMX6QDL_CLK_PRE_AXI 258
#define IMX6QDL_CLK_MLB_SEL 259
#define IMX6QDL_CLK_MLB_PODF 260
#define IMX6QDL_CLK_END 261
#define IMX6QDL_CLK_EPIT1 261
#define IMX6QDL_CLK_EPIT2 262
#define IMX6QDL_CLK_END 263
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

6
include/dt-bindings/clock/imx6sx-clock.h
View File

@@ -275,6 +275,10 @@
#define IMX6SX_PLL6_BYPASS 262
#define IMX6SX_PLL7_BYPASS 263
#define IMX6SX_CLK_SPDIF_GCLK 264
#define IMX6SX_CLK_CLK_END 265
#define IMX6SX_CLK_LVDS2_SEL 265
#define IMX6SX_CLK_LVDS2_OUT 266
#define IMX6SX_CLK_LVDS2_IN 267
#define IMX6SX_CLK_ANACLK2 268
#define IMX6SX_CLK_CLK_END 269
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */

33
include/dt-bindings/clock/imx6ul-clock.h
View File

@@ -235,20 +235,27 @@
#define IMX6UL_CLK_CSI_PODF 222
#define IMX6UL_CLK_PLL3_120M 223
#define IMX6UL_CLK_KPP 224
#define IMX6UL_CLK_CKO1_SEL 225
#define IMX6UL_CLK_CKO1_PODF 226
#define IMX6UL_CLK_CKO1 227
#define IMX6UL_CLK_CKO2_SEL 228
#define IMX6UL_CLK_CKO2_PODF 229
#define IMX6UL_CLK_CKO2 230
#define IMX6UL_CLK_CKO 231
/* For i.MX6ULL */
#define IMX6ULL_CLK_ESAI_PRED 225
#define IMX6ULL_CLK_ESAI_PODF 226
#define IMX6ULL_CLK_ESAI_EXTAL 227
#define IMX6ULL_CLK_ESAI_MEM 228
#define IMX6ULL_CLK_ESAI_IPG 229
#define IMX6ULL_CLK_DCP_CLK 230
#define IMX6ULL_CLK_EPDC_PRE_SEL 231
#define IMX6ULL_CLK_EPDC_SEL 232
#define IMX6ULL_CLK_EPDC_PODF 233
#define IMX6ULL_CLK_EPDC_ACLK 234
#define IMX6ULL_CLK_EPDC_PIX 235
#define IMX6ULL_CLK_ESAI_SEL 236
#define IMX6UL_CLK_END 237
#define IMX6ULL_CLK_ESAI_PRED 232
#define IMX6ULL_CLK_ESAI_PODF 233
#define IMX6ULL_CLK_ESAI_EXTAL 234
#define IMX6ULL_CLK_ESAI_MEM 235
#define IMX6ULL_CLK_ESAI_IPG 236
#define IMX6ULL_CLK_DCP_CLK 237
#define IMX6ULL_CLK_EPDC_PRE_SEL 238
#define IMX6ULL_CLK_EPDC_SEL 239
#define IMX6ULL_CLK_EPDC_PODF 240
#define IMX6ULL_CLK_EPDC_ACLK 241
#define IMX6ULL_CLK_EPDC_PIX 242
#define IMX6ULL_CLK_ESAI_SEL 243
#define IMX6UL_CLK_END 244
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */

4
include/dt-bindings/clock/imx7d-clock.h
View File

@@ -168,7 +168,7 @@
#define IMX7D_SPDIF_ROOT_SRC 155
#define IMX7D_SPDIF_ROOT_CG 156
#define IMX7D_SPDIF_ROOT_DIV 157
#define IMX7D_ENET1_REF_ROOT_CLK 158
#define IMX7D_ENET1_IPG_ROOT_CLK 158
#define IMX7D_ENET1_REF_ROOT_SRC 159
#define IMX7D_ENET1_REF_ROOT_CG 160
#define IMX7D_ENET1_REF_ROOT_DIV 161
@@ -176,7 +176,7 @@
#define IMX7D_ENET1_TIME_ROOT_SRC 163
#define IMX7D_ENET1_TIME_ROOT_CG 164
#define IMX7D_ENET1_TIME_ROOT_DIV 165
#define IMX7D_ENET2_REF_ROOT_CLK 166
#define IMX7D_ENET2_IPG_ROOT_CLK 166
#define IMX7D_ENET2_REF_ROOT_SRC 167
#define IMX7D_ENET2_REF_ROOT_CG 168
#define IMX7D_ENET2_REF_ROOT_DIV 169

1
include/dt-bindings/clock/meson8b-clkc.h
View File

@@ -102,5 +102,6 @@
#define CLKID_MPLL0 93
#define CLKID_MPLL1 94
#define CLKID_MPLL2 95
#define CLKID_NAND_CLK 112
#endif /* __MESON8B_CLKC_H */

20
include/dt-bindings/clock/mt2701-clk.h
View File

@@ -171,13 +171,12 @@
#define CLK_TOP_8BDAC 151
#define CLK_TOP_WBG_DIG_416M 152
#define CLK_TOP_DPI 153
#define CLK_TOP_HDMITX_CLKDIG_CTS 154
#define CLK_TOP_DSI0_LNTC_DSI 155
#define CLK_TOP_AUD_EXT1 156
#define CLK_TOP_AUD_EXT2 157
#define CLK_TOP_NFI1X_PAD 158
#define CLK_TOP_AXISEL_D4 159
#define CLK_TOP_NR 160
#define CLK_TOP_DSI0_LNTC_DSI 154
#define CLK_TOP_AUD_EXT1 155
#define CLK_TOP_AUD_EXT2 156
#define CLK_TOP_NFI1X_PAD 157
#define CLK_TOP_AXISEL_D4 158
#define CLK_TOP_NR 159
/* APMIXEDSYS */
@@ -194,7 +193,8 @@
#define CLK_APMIXED_HADDS2PLL 11
#define CLK_APMIXED_AUD2PLL 12
#define CLK_APMIXED_TVD2PLL 13
#define CLK_APMIXED_NR 14
#define CLK_APMIXED_HDMI_REF 14
#define CLK_APMIXED_NR 15
/* DDRPHY */
@@ -431,6 +431,10 @@
#define CLK_ETHSYS_CRYPTO 8
#define CLK_ETHSYS_NR 9
/* G3DSYS */
#define CLK_G3DSYS_CORE 1
#define CLK_G3DSYS_NR 2
/* BDP */
#define CLK_BDP_BRG_BA 1

44
include/dt-bindings/clock/nuvoton,npcm7xx-clock.h Normal file
View File

@@ -0,0 +1,44 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Nuvoton NPCM7xx Clock Generator binding
* clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
*
* Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
*
*/
#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
#define __DT_BINDINGS_CLOCK_NPCM7XX_H
#define NPCM7XX_CLK_CPU 0
#define NPCM7XX_CLK_GFX_PIXEL 1
#define NPCM7XX_CLK_MC 2
#define NPCM7XX_CLK_ADC 3
#define NPCM7XX_CLK_AHB 4
#define NPCM7XX_CLK_TIMER 5
#define NPCM7XX_CLK_UART 6
#define NPCM7XX_CLK_MMC 7
#define NPCM7XX_CLK_SPI3 8
#define NPCM7XX_CLK_PCI 9
#define NPCM7XX_CLK_AXI 10
#define NPCM7XX_CLK_APB4 11
#define NPCM7XX_CLK_APB3 12
#define NPCM7XX_CLK_APB2 13
#define NPCM7XX_CLK_APB1 14
#define NPCM7XX_CLK_APB5 15
#define NPCM7XX_CLK_CLKOUT 16
#define NPCM7XX_CLK_GFX 17
#define NPCM7XX_CLK_SU 18
#define NPCM7XX_CLK_SU48 19
#define NPCM7XX_CLK_SDHC 20
#define NPCM7XX_CLK_SPI0 21
#define NPCM7XX_CLK_SPIX 22
#define NPCM7XX_CLK_REFCLK 23
#define NPCM7XX_CLK_SYSBYPCK 24
#define NPCM7XX_CLK_MCBYPCK 25
#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1)
#endif

208
include/dt-bindings/clock/qcom,gcc-msm8998.h Normal file
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@@ -0,0 +1,208 @@
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11
#define BLSP1_UART1_APPS_CLK_SRC 12
#define BLSP1_UART2_APPS_CLK_SRC 13
#define BLSP1_UART3_APPS_CLK_SRC 14
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22
#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23
#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24
#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25
#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26
#define BLSP2_UART1_APPS_CLK_SRC 27
#define BLSP2_UART2_APPS_CLK_SRC 28
#define BLSP2_UART3_APPS_CLK_SRC 29
#define GCC_AGGRE1_NOC_XO_CLK 30
#define GCC_AGGRE1_UFS_AXI_CLK 31
#define GCC_AGGRE1_USB3_AXI_CLK 32
#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33
#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34
#define GCC_BIMC_HMSS_AXI_CLK 35
#define GCC_BIMC_MSS_Q6_AXI_CLK 36
#define GCC_BLSP1_AHB_CLK 37
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49
#define GCC_BLSP1_SLEEP_CLK 50
#define GCC_BLSP1_UART1_APPS_CLK 51
#define GCC_BLSP1_UART2_APPS_CLK 52
#define GCC_BLSP1_UART3_APPS_CLK 53
#define GCC_BLSP2_AHB_CLK 54
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62
#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63
#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64
#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65
#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66
#define GCC_BLSP2_SLEEP_CLK 67
#define GCC_BLSP2_UART1_APPS_CLK 68
#define GCC_BLSP2_UART2_APPS_CLK 69
#define GCC_BLSP2_UART3_APPS_CLK 70
#define GCC_CFG_NOC_USB3_AXI_CLK 71
#define GCC_GP1_CLK 72
#define GCC_GP2_CLK 73
#define GCC_GP3_CLK 74
#define GCC_GPU_BIMC_GFX_CLK 75
#define GCC_GPU_BIMC_GFX_SRC_CLK 76
#define GCC_GPU_CFG_AHB_CLK 77
#define GCC_GPU_SNOC_DVM_GFX_CLK 78
#define GCC_HMSS_AHB_CLK 79
#define GCC_HMSS_AT_CLK 80
#define GCC_HMSS_DVM_BUS_CLK 81
#define GCC_HMSS_RBCPR_CLK 82
#define GCC_HMSS_TRIG_CLK 83
#define GCC_LPASS_AT_CLK 84
#define GCC_LPASS_TRIG_CLK 85
#define GCC_MMSS_NOC_CFG_AHB_CLK 86
#define GCC_MMSS_QM_AHB_CLK 87
#define GCC_MMSS_QM_CORE_CLK 88
#define GCC_MMSS_SYS_NOC_AXI_CLK 89
#define GCC_MSS_AT_CLK 90
#define GCC_PCIE_0_AUX_CLK 91
#define GCC_PCIE_0_CFG_AHB_CLK 92
#define GCC_PCIE_0_MSTR_AXI_CLK 93
#define GCC_PCIE_0_PIPE_CLK 94
#define GCC_PCIE_0_SLV_AXI_CLK 95
#define GCC_PCIE_PHY_AUX_CLK 96
#define GCC_PDM2_CLK 97
#define GCC_PDM_AHB_CLK 98
#define GCC_PDM_XO4_CLK 99
#define GCC_PRNG_AHB_CLK 100
#define GCC_SDCC2_AHB_CLK 101
#define GCC_SDCC2_APPS_CLK 102
#define GCC_SDCC4_AHB_CLK 103
#define GCC_SDCC4_APPS_CLK 104
#define GCC_TSIF_AHB_CLK 105
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106
#define GCC_TSIF_REF_CLK 107
#define GCC_UFS_AHB_CLK 108
#define GCC_UFS_AXI_CLK 109
#define GCC_UFS_ICE_CORE_CLK 110
#define GCC_UFS_PHY_AUX_CLK 111
#define GCC_UFS_RX_SYMBOL_0_CLK 112
#define GCC_UFS_RX_SYMBOL_1_CLK 113
#define GCC_UFS_TX_SYMBOL_0_CLK 114
#define GCC_UFS_UNIPRO_CORE_CLK 115
#define GCC_USB30_MASTER_CLK 116
#define GCC_USB30_MOCK_UTMI_CLK 117
#define GCC_USB30_SLEEP_CLK 118
#define GCC_USB3_PHY_AUX_CLK 119
#define GCC_USB3_PHY_PIPE_CLK 120
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121
#define GP1_CLK_SRC 122
#define GP2_CLK_SRC 123
#define GP3_CLK_SRC 124
#define GPLL0 125
#define GPLL0_OUT_EVEN 126
#define GPLL0_OUT_MAIN 127
#define GPLL0_OUT_ODD 128
#define GPLL0_OUT_TEST 129
#define GPLL1 130
#define GPLL1_OUT_EVEN 131
#define GPLL1_OUT_MAIN 132
#define GPLL1_OUT_ODD 133
#define GPLL1_OUT_TEST 134
#define GPLL2 135
#define GPLL2_OUT_EVEN 136
#define GPLL2_OUT_MAIN 137
#define GPLL2_OUT_ODD 138
#define GPLL2_OUT_TEST 139
#define GPLL3 140
#define GPLL3_OUT_EVEN 141
#define GPLL3_OUT_MAIN 142
#define GPLL3_OUT_ODD 143
#define GPLL3_OUT_TEST 144
#define GPLL4 145
#define GPLL4_OUT_EVEN 146
#define GPLL4_OUT_MAIN 147
#define GPLL4_OUT_ODD 148
#define GPLL4_OUT_TEST 149
#define GPLL6 150
#define GPLL6_OUT_EVEN 151
#define GPLL6_OUT_MAIN 152
#define GPLL6_OUT_ODD 153
#define GPLL6_OUT_TEST 154
#define HMSS_AHB_CLK_SRC 155
#define HMSS_RBCPR_CLK_SRC 156
#define PCIE_AUX_CLK_SRC 157
#define PDM2_CLK_SRC 158
#define SDCC2_APPS_CLK_SRC 159
#define SDCC4_APPS_CLK_SRC 160
#define TSIF_REF_CLK_SRC 161
#define UFS_AXI_CLK_SRC 162
#define USB30_MASTER_CLK_SRC 163
#define USB30_MOCK_UTMI_CLK_SRC 164
#define USB3_PHY_AUX_CLK_SRC 165
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
#define USB_30_GDSC 2
#define GCC_BLSP1_QUP1_BCR 0
#define GCC_BLSP1_QUP2_BCR 1
#define GCC_BLSP1_QUP3_BCR 2
#define GCC_BLSP1_QUP4_BCR 3
#define GCC_BLSP1_QUP5_BCR 4
#define GCC_BLSP1_QUP6_BCR 5
#define GCC_BLSP2_QUP1_BCR 6
#define GCC_BLSP2_QUP2_BCR 7
#define GCC_BLSP2_QUP3_BCR 8
#define GCC_BLSP2_QUP4_BCR 9
#define GCC_BLSP2_QUP5_BCR 10
#define GCC_BLSP2_QUP6_BCR 11
#define GCC_PCIE_0_BCR 12
#define GCC_PDM_BCR 13
#define GCC_SDCC2_BCR 14
#define GCC_SDCC4_BCR 15
#define GCC_TSIF_BCR 16
#define GCC_UFS_BCR 17
#define GCC_USB_30_BCR 18
#endif

239
include/dt-bindings/clock/qcom,gcc-sdm845.h Normal file
View File

@@ -0,0 +1,239 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
/* GCC clock registers */
#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
#define GCC_BOOT_ROM_AHB_CLK 5
#define GCC_CAMERA_AHB_CLK 6
#define GCC_CAMERA_AXI_CLK 7
#define GCC_CAMERA_XO_CLK 8
#define GCC_CE1_AHB_CLK 9
#define GCC_CE1_AXI_CLK 10
#define GCC_CE1_CLK 11
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
#define GCC_CPUSS_AHB_CLK 14
#define GCC_CPUSS_AHB_CLK_SRC 15
#define GCC_CPUSS_RBCPR_CLK 16
#define GCC_CPUSS_RBCPR_CLK_SRC 17
#define GCC_DDRSS_GPU_AXI_CLK 18
#define GCC_DISP_AHB_CLK 19
#define GCC_DISP_AXI_CLK 20
#define GCC_DISP_GPLL0_CLK_SRC 21
#define GCC_DISP_GPLL0_DIV_CLK_SRC 22
#define GCC_DISP_XO_CLK 23
#define GCC_GP1_CLK 24
#define GCC_GP1_CLK_SRC 25
#define GCC_GP2_CLK 26
#define GCC_GP2_CLK_SRC 27
#define GCC_GP3_CLK 28
#define GCC_GP3_CLK_SRC 29
#define GCC_GPU_CFG_AHB_CLK 30
#define GCC_GPU_GPLL0_CLK_SRC 31
#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
#define GCC_GPU_MEMNOC_GFX_CLK 33
#define GCC_GPU_SNOC_DVM_GFX_CLK 34
#define GCC_MSS_AXIS2_CLK 35
#define GCC_MSS_CFG_AHB_CLK 36
#define GCC_MSS_GPLL0_DIV_CLK_SRC 37
#define GCC_MSS_MFAB_AXIS_CLK 38
#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39
#define GCC_MSS_SNOC_AXI_CLK 40
#define GCC_PCIE_0_AUX_CLK 41
#define GCC_PCIE_0_AUX_CLK_SRC 42
#define GCC_PCIE_0_CFG_AHB_CLK 43
#define GCC_PCIE_0_CLKREF_CLK 44
#define GCC_PCIE_0_MSTR_AXI_CLK 45
#define GCC_PCIE_0_PIPE_CLK 46
#define GCC_PCIE_0_SLV_AXI_CLK 47
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
#define GCC_PCIE_1_AUX_CLK 49
#define GCC_PCIE_1_AUX_CLK_SRC 50
#define GCC_PCIE_1_CFG_AHB_CLK 51
#define GCC_PCIE_1_CLKREF_CLK 52
#define GCC_PCIE_1_MSTR_AXI_CLK 53
#define GCC_PCIE_1_PIPE_CLK 54
#define GCC_PCIE_1_SLV_AXI_CLK 55
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56
#define GCC_PCIE_PHY_AUX_CLK 57
#define GCC_PCIE_PHY_REFGEN_CLK 58
#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59
#define GCC_PDM2_CLK 60
#define GCC_PDM2_CLK_SRC 61
#define GCC_PDM_AHB_CLK 62
#define GCC_PDM_XO4_CLK 63
#define GCC_PRNG_AHB_CLK 64
#define GCC_QMIP_CAMERA_AHB_CLK 65
#define GCC_QMIP_DISP_AHB_CLK 66
#define GCC_QMIP_VIDEO_AHB_CLK 67
#define GCC_QUPV3_WRAP0_S0_CLK 68
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
#define GCC_QUPV3_WRAP0_S1_CLK 70
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
#define GCC_QUPV3_WRAP0_S2_CLK 72
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
#define GCC_QUPV3_WRAP0_S3_CLK 74
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
#define GCC_QUPV3_WRAP0_S4_CLK 76
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77
#define GCC_QUPV3_WRAP0_S5_CLK 78
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79
#define GCC_QUPV3_WRAP0_S6_CLK 80
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81
#define GCC_QUPV3_WRAP0_S7_CLK 82
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83
#define GCC_QUPV3_WRAP1_S0_CLK 84
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85
#define GCC_QUPV3_WRAP1_S1_CLK 86
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87
#define GCC_QUPV3_WRAP1_S2_CLK 88
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89
#define GCC_QUPV3_WRAP1_S3_CLK 90
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91
#define GCC_QUPV3_WRAP1_S4_CLK 92
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93
#define GCC_QUPV3_WRAP1_S5_CLK 94
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95
#define GCC_QUPV3_WRAP1_S6_CLK 96
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97
#define GCC_QUPV3_WRAP1_S7_CLK 98
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103
#define GCC_SDCC2_AHB_CLK 104
#define GCC_SDCC2_APPS_CLK 105
#define GCC_SDCC2_APPS_CLK_SRC 106
#define GCC_SDCC4_AHB_CLK 107
#define GCC_SDCC4_APPS_CLK 108
#define GCC_SDCC4_APPS_CLK_SRC 109
#define GCC_SYS_NOC_CPUSS_AHB_CLK 110
#define GCC_TSIF_AHB_CLK 111
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112
#define GCC_TSIF_REF_CLK 113
#define GCC_TSIF_REF_CLK_SRC 114
#define GCC_UFS_CARD_AHB_CLK 115
#define GCC_UFS_CARD_AXI_CLK 116
#define GCC_UFS_CARD_AXI_CLK_SRC 117
#define GCC_UFS_CARD_CLKREF_CLK 118
#define GCC_UFS_CARD_ICE_CORE_CLK 119
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120
#define GCC_UFS_CARD_PHY_AUX_CLK 121
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127
#define GCC_UFS_MEM_CLKREF_CLK 128
#define GCC_UFS_PHY_AHB_CLK 129
#define GCC_UFS_PHY_AXI_CLK 130
#define GCC_UFS_PHY_AXI_CLK_SRC 131
#define GCC_UFS_PHY_ICE_CORE_CLK 132
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133
#define GCC_UFS_PHY_PHY_AUX_CLK 134
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140
#define GCC_USB30_PRIM_MASTER_CLK 141
#define GCC_USB30_PRIM_MASTER_CLK_SRC 142
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144
#define GCC_USB30_PRIM_SLEEP_CLK 145
#define GCC_USB30_SEC_MASTER_CLK 146
#define GCC_USB30_SEC_MASTER_CLK_SRC 147
#define GCC_USB30_SEC_MOCK_UTMI_CLK 148
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149
#define GCC_USB30_SEC_SLEEP_CLK 150
#define GCC_USB3_PRIM_CLKREF_CLK 151
#define GCC_USB3_PRIM_PHY_AUX_CLK 152
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154
#define GCC_USB3_PRIM_PHY_PIPE_CLK 155
#define GCC_USB3_SEC_CLKREF_CLK 156
#define GCC_USB3_SEC_PHY_AUX_CLK 157
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158
#define GCC_USB3_SEC_PHY_PIPE_CLK 159
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
#define GCC_VIDEO_AHB_CLK 162
#define GCC_VIDEO_AXI_CLK 163
#define GCC_VIDEO_XO_CLK 164
#define GPLL0 165
#define GPLL0_OUT_EVEN 166
#define GPLL0_OUT_MAIN 167
#define GCC_GPU_IREF_CLK 168
#define GCC_SDCC1_AHB_CLK 169
#define GCC_SDCC1_APPS_CLK 170
#define GCC_SDCC1_ICE_CORE_CLK 171
#define GCC_SDCC1_APPS_CLK_SRC 172
#define GCC_SDCC1_ICE_CORE_CLK_SRC 173
#define GCC_APC_VS_CLK 174
#define GCC_GPU_VS_CLK 175
#define GCC_MSS_VS_CLK 176
#define GCC_VDDA_VS_CLK 177
#define GCC_VDDCX_VS_CLK 178
#define GCC_VDDMX_VS_CLK 179
#define GCC_VS_CTRL_AHB_CLK 180
#define GCC_VS_CTRL_CLK 181
#define GCC_VS_CTRL_CLK_SRC 182
#define GCC_VSENSOR_CLK_SRC 183
#define GPLL4 184
/* GCC Resets */
#define GCC_MMSS_BCR 0
#define GCC_PCIE_0_BCR 1
#define GCC_PCIE_1_BCR 2
#define GCC_PCIE_PHY_BCR 3
#define GCC_PDM_BCR 4
#define GCC_PRNG_BCR 5
#define GCC_QUPV3_WRAPPER_0_BCR 6
#define GCC_QUPV3_WRAPPER_1_BCR 7
#define GCC_QUSB2PHY_PRIM_BCR 8
#define GCC_QUSB2PHY_SEC_BCR 9
#define GCC_SDCC2_BCR 10
#define GCC_SDCC4_BCR 11
#define GCC_TSIF_BCR 12
#define GCC_UFS_CARD_BCR 13
#define GCC_UFS_PHY_BCR 14
#define GCC_USB30_PRIM_BCR 15
#define GCC_USB30_SEC_BCR 16
#define GCC_USB3_PHY_PRIM_BCR 17
#define GCC_USB3PHY_PHY_PRIM_BCR 18
#define GCC_USB3_DP_PHY_PRIM_BCR 19
#define GCC_USB3_PHY_SEC_BCR 20
#define GCC_USB3PHY_PHY_SEC_BCR 21
#define GCC_USB3_DP_PHY_SEC_BCR 22
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
#define GCC_PCIE_0_PHY_BCR 24
#define GCC_PCIE_1_PHY_BCR 25
/* GCC GDSCRs */
#define PCIE_0_GDSC 0
#define PCIE_1_GDSC 1
#define UFS_CARD_GDSC 2
#define UFS_PHY_GDSC 3
#define USB30_PRIM_GDSC 4
#define USB30_SEC_GDSC 5
#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6
#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7
#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8
#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12
#endif

22
include/dt-bindings/clock/qcom,rpmh.h Normal file
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@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
#define _DT_BINDINGS_CLK_MSM_RPMH_H
/* RPMh controlled clocks */
#define RPMH_CXO_CLK 0
#define RPMH_CXO_CLK_A 1
#define RPMH_LN_BB_CLK2 2
#define RPMH_LN_BB_CLK2_A 3
#define RPMH_LN_BB_CLK3 4
#define RPMH_LN_BB_CLK3_A 5
#define RPMH_RF_CLK1 6
#define RPMH_RF_CLK1_A 7
#define RPMH_RF_CLK2 8
#define RPMH_RF_CLK2_A 9
#define RPMH_RF_CLK3 10
#define RPMH_RF_CLK3_A 11
#endif

35
include/dt-bindings/clock/qcom,videocc-sdm845.h Normal file
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@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
/* VIDEO_CC clock registers */
#define VIDEO_CC_APB_CLK 0
#define VIDEO_CC_AT_CLK 1
#define VIDEO_CC_QDSS_TRIG_CLK 2
#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3
#define VIDEO_CC_VCODEC0_AXI_CLK 4
#define VIDEO_CC_VCODEC0_CORE_CLK 5
#define VIDEO_CC_VCODEC1_AXI_CLK 6
#define VIDEO_CC_VCODEC1_CORE_CLK 7
#define VIDEO_CC_VENUS_AHB_CLK 8
#define VIDEO_CC_VENUS_CLK_SRC 9
#define VIDEO_CC_VENUS_CTL_AXI_CLK 10
#define VIDEO_CC_VENUS_CTL_CORE_CLK 11
#define VIDEO_PLL0 12
/* VIDEO_CC Resets */
#define VIDEO_CC_VENUS_BCR 0
#define VIDEO_CC_VCODEC0_BCR 1
#define VIDEO_CC_VCODEC1_BCR 2
#define VIDEO_CC_INTERFACE_BCR 3
/* VIDEO_CC GDSCRs */
#define VENUS_GDSC 0
#define VCODEC0_GDSC 1
#define VCODEC1_GDSC 2
#endif

36
include/dt-bindings/clock/r8a77470-cpg-mssr.h Normal file
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@@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a77470 CPG Core Clocks */
#define R8A77470_CLK_Z2 0
#define R8A77470_CLK_ZTR 1
#define R8A77470_CLK_ZTRD2 2
#define R8A77470_CLK_ZT 3
#define R8A77470_CLK_ZX 4
#define R8A77470_CLK_ZS 5
#define R8A77470_CLK_HP 6
#define R8A77470_CLK_B 7
#define R8A77470_CLK_LB 8
#define R8A77470_CLK_P 9
#define R8A77470_CLK_CL 10
#define R8A77470_CLK_CP 11
#define R8A77470_CLK_M2 12
#define R8A77470_CLK_ZB3 13
#define R8A77470_CLK_SDH 14
#define R8A77470_CLK_SD0 15
#define R8A77470_CLK_SD1 16
#define R8A77470_CLK_SD2 17
#define R8A77470_CLK_MP 18
#define R8A77470_CLK_QSPI 19
#define R8A77470_CLK_CPEX 20
#define R8A77470_CLK_RCAN 21
#define R8A77470_CLK_R 22
#define R8A77470_CLK_OSC 23
#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */

62
include/dt-bindings/clock/r8a77990-cpg-mssr.h Normal file
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@@ -0,0 +1,62 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a77990 CPG Core Clocks */
#define R8A77990_CLK_Z2 0
#define R8A77990_CLK_ZR 1
#define R8A77990_CLK_ZG 2
#define R8A77990_CLK_ZTR 3
#define R8A77990_CLK_ZT 4
#define R8A77990_CLK_ZX 5
#define R8A77990_CLK_S0D1 6
#define R8A77990_CLK_S0D3 7
#define R8A77990_CLK_S0D6 8
#define R8A77990_CLK_S0D12 9
#define R8A77990_CLK_S0D24 10
#define R8A77990_CLK_S1D1 11
#define R8A77990_CLK_S1D2 12
#define R8A77990_CLK_S1D4 13
#define R8A77990_CLK_S2D1 14
#define R8A77990_CLK_S2D2 15
#define R8A77990_CLK_S2D4 16
#define R8A77990_CLK_S3D1 17
#define R8A77990_CLK_S3D2 18
#define R8A77990_CLK_S3D4 19
#define R8A77990_CLK_S0D6C 20
#define R8A77990_CLK_S3D1C 21
#define R8A77990_CLK_S3D2C 22
#define R8A77990_CLK_S3D4C 23
#define R8A77990_CLK_LB 24
#define R8A77990_CLK_CL 25
#define R8A77990_CLK_ZB3 26
#define R8A77990_CLK_ZB3D2 27
#define R8A77990_CLK_CR 28
#define R8A77990_CLK_CRD2 29
#define R8A77990_CLK_SD0H 30
#define R8A77990_CLK_SD0 31
#define R8A77990_CLK_SD1H 32
#define R8A77990_CLK_SD1 33
#define R8A77990_CLK_SD3H 34
#define R8A77990_CLK_SD3 35
#define R8A77990_CLK_RPC 36
#define R8A77990_CLK_RPCD2 37
#define R8A77990_CLK_ZA2 38
#define R8A77990_CLK_ZA8 39
#define R8A77990_CLK_Z2D 40
#define R8A77990_CLK_CANFD 41
#define R8A77990_CLK_MSO 42
#define R8A77990_CLK_R 43
#define R8A77990_CLK_OSC 44
#define R8A77990_CLK_LV0 45
#define R8A77990_CLK_LV1 46
#define R8A77990_CLK_CSI0 47
#define R8A77990_CLK_CP 48
#define R8A77990_CLK_CPEX 49
#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */

4
include/dt-bindings/clock/stm32mp1-clks.h
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@@ -76,7 +76,7 @@
#define I2C6 63
#define USART1 64
#define RTCAPB 65
#define TZC 66
#define TZC1 66
#define TZPC 67
#define IWDG1 68
#define BSEC 69
@@ -123,6 +123,7 @@
#define CRC1 110
#define USBH 111
#define ETHSTP 112
#define TZC2 113
/* Kernel clocks */
#define SDMMC1_K 118
@@ -228,7 +229,6 @@
#define CK_MCO2 212
/* TRACE & DEBUG clocks */
#define DBG 213
#define CK_DBG 214
#define CK_TRACE 215

24
include/dt-bindings/clock/sun50i-h6-r-ccu.h Normal file
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@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
#define CLK_AR100 0
#define CLK_R_APB1 2
#define CLK_R_APB1_TIMER 4
#define CLK_R_APB1_TWD 5
#define CLK_R_APB1_PWM 6
#define CLK_R_APB2_UART 7
#define CLK_R_APB2_I2C 8
#define CLK_R_APB1_IR 9
#define CLK_R_APB1_W1 10
#define CLK_IR 11
#define CLK_W1 12
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */

11
include/dt-bindings/clock/sun8i-tcon-top.h Normal file
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@@ -0,0 +1,11 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
#define CLK_TCON_TOP_TV0 0
#define CLK_TCON_TOP_TV1 1
#define CLK_TCON_TOP_DSI 2
#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */

49
include/dt-bindings/dma/jz4780-dma.h Normal file
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@@ -0,0 +1,49 @@
#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
#define __DT_BINDINGS_DMA_JZ4780_DMA_H__
/*
* Request type numbers for the JZ4780 DMA controller (written to the DRTn
* register for the channel).
*/
#define JZ4780_DMA_I2S1_TX 0x4
#define JZ4780_DMA_I2S1_RX 0x5
#define JZ4780_DMA_I2S0_TX 0x6
#define JZ4780_DMA_I2S0_RX 0x7
#define JZ4780_DMA_AUTO 0x8
#define JZ4780_DMA_SADC_RX 0x9
#define JZ4780_DMA_UART4_TX 0xc
#define JZ4780_DMA_UART4_RX 0xd
#define JZ4780_DMA_UART3_TX 0xe
#define JZ4780_DMA_UART3_RX 0xf
#define JZ4780_DMA_UART2_TX 0x10
#define JZ4780_DMA_UART2_RX 0x11
#define JZ4780_DMA_UART1_TX 0x12
#define JZ4780_DMA_UART1_RX 0x13
#define JZ4780_DMA_UART0_TX 0x14
#define JZ4780_DMA_UART0_RX 0x15
#define JZ4780_DMA_SSI0_TX 0x16
#define JZ4780_DMA_SSI0_RX 0x17
#define JZ4780_DMA_SSI1_TX 0x18
#define JZ4780_DMA_SSI1_RX 0x19
#define JZ4780_DMA_MSC0_TX 0x1a
#define JZ4780_DMA_MSC0_RX 0x1b
#define JZ4780_DMA_MSC1_TX 0x1c
#define JZ4780_DMA_MSC1_RX 0x1d
#define JZ4780_DMA_MSC2_TX 0x1e
#define JZ4780_DMA_MSC2_RX 0x1f
#define JZ4780_DMA_PCM0_TX 0x20
#define JZ4780_DMA_PCM0_RX 0x21
#define JZ4780_DMA_SMB0_TX 0x24
#define JZ4780_DMA_SMB0_RX 0x25
#define JZ4780_DMA_SMB1_TX 0x26
#define JZ4780_DMA_SMB1_RX 0x27
#define JZ4780_DMA_SMB2_TX 0x28
#define JZ4780_DMA_SMB2_RX 0x29
#define JZ4780_DMA_SMB3_TX 0x2a
#define JZ4780_DMA_SMB3_RX 0x2b
#define JZ4780_DMA_SMB4_TX 0x2c
#define JZ4780_DMA_SMB4_RX 0x2d
#define JZ4780_DMA_DES_TX 0x2e
#define JZ4780_DMA_DES_RX 0x2f
#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */

17
include/dt-bindings/memory/tegra114-mc.h
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@@ -23,4 +23,21 @@
#define TEGRA_SWGROUP_EMUCIF 18
#define TEGRA_SWGROUP_TSEC 19
#define TEGRA114_MC_RESET_AVPC 0
#define TEGRA114_MC_RESET_DC 1
#define TEGRA114_MC_RESET_DCB 2
#define TEGRA114_MC_RESET_EPP 3
#define TEGRA114_MC_RESET_2D 4
#define TEGRA114_MC_RESET_HC 5
#define TEGRA114_MC_RESET_HDA 6
#define TEGRA114_MC_RESET_ISP 7
#define TEGRA114_MC_RESET_MPCORE 8
#define TEGRA114_MC_RESET_MPCORELP 9
#define TEGRA114_MC_RESET_MPE 10
#define TEGRA114_MC_RESET_3D 11
#define TEGRA114_MC_RESET_3D2 12
#define TEGRA114_MC_RESET_PPCS 13
#define TEGRA114_MC_RESET_VDE 14
#define TEGRA114_MC_RESET_VI 15
#endif

25
include/dt-bindings/memory/tegra124-mc.h
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@@ -29,4 +29,29 @@
#define TEGRA_SWGROUP_VIC 24
#define TEGRA_SWGROUP_VI 25
#define TEGRA124_MC_RESET_AFI 0
#define TEGRA124_MC_RESET_AVPC 1
#define TEGRA124_MC_RESET_DC 2
#define TEGRA124_MC_RESET_DCB 3
#define TEGRA124_MC_RESET_HC 4
#define TEGRA124_MC_RESET_HDA 5
#define TEGRA124_MC_RESET_ISP2 6
#define TEGRA124_MC_RESET_MPCORE 7
#define TEGRA124_MC_RESET_MPCORELP 8
#define TEGRA124_MC_RESET_MSENC 9
#define TEGRA124_MC_RESET_PPCS 10
#define TEGRA124_MC_RESET_SATA 11
#define TEGRA124_MC_RESET_VDE 12
#define TEGRA124_MC_RESET_VI 13
#define TEGRA124_MC_RESET_VIC 14
#define TEGRA124_MC_RESET_XUSB_HOST 15
#define TEGRA124_MC_RESET_XUSB_DEV 16
#define TEGRA124_MC_RESET_TSEC 17
#define TEGRA124_MC_RESET_SDMMC1 18
#define TEGRA124_MC_RESET_SDMMC2 19
#define TEGRA124_MC_RESET_SDMMC3 20
#define TEGRA124_MC_RESET_SDMMC4 21
#define TEGRA124_MC_RESET_ISP2B 22
#define TEGRA124_MC_RESET_GPU 23
#endif

21
include/dt-bindings/memory/tegra20-mc.h Normal file
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@@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
#define DT_BINDINGS_MEMORY_TEGRA20_MC_H
#define TEGRA20_MC_RESET_AVPC 0
#define TEGRA20_MC_RESET_DC 1
#define TEGRA20_MC_RESET_DCB 2
#define TEGRA20_MC_RESET_EPP 3
#define TEGRA20_MC_RESET_2D 4
#define TEGRA20_MC_RESET_HC 5
#define TEGRA20_MC_RESET_ISP 6
#define TEGRA20_MC_RESET_MPCORE 7
#define TEGRA20_MC_RESET_MPEA 8
#define TEGRA20_MC_RESET_MPEB 9
#define TEGRA20_MC_RESET_MPEC 10
#define TEGRA20_MC_RESET_3D 11
#define TEGRA20_MC_RESET_PPCS 12
#define TEGRA20_MC_RESET_VDE 13
#define TEGRA20_MC_RESET_VI 14
#endif

31
include/dt-bindings/memory/tegra210-mc.h
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@@ -34,4 +34,35 @@
#define TEGRA_SWGROUP_ETR 29
#define TEGRA_SWGROUP_TSECB 30
#define TEGRA210_MC_RESET_AFI 0
#define TEGRA210_MC_RESET_AVPC 1
#define TEGRA210_MC_RESET_DC 2
#define TEGRA210_MC_RESET_DCB 3
#define TEGRA210_MC_RESET_HC 4
#define TEGRA210_MC_RESET_HDA 5
#define TEGRA210_MC_RESET_ISP2 6
#define TEGRA210_MC_RESET_MPCORE 7
#define TEGRA210_MC_RESET_NVENC 8
#define TEGRA210_MC_RESET_PPCS 9
#define TEGRA210_MC_RESET_SATA 10
#define TEGRA210_MC_RESET_VI 11
#define TEGRA210_MC_RESET_VIC 12
#define TEGRA210_MC_RESET_XUSB_HOST 13
#define TEGRA210_MC_RESET_XUSB_DEV 14
#define TEGRA210_MC_RESET_A9AVP 15
#define TEGRA210_MC_RESET_TSEC 16
#define TEGRA210_MC_RESET_SDMMC1 17
#define TEGRA210_MC_RESET_SDMMC2 18
#define TEGRA210_MC_RESET_SDMMC3 19
#define TEGRA210_MC_RESET_SDMMC4 20
#define TEGRA210_MC_RESET_ISP2B 21
#define TEGRA210_MC_RESET_GPU 22
#define TEGRA210_MC_RESET_NVDEC 23
#define TEGRA210_MC_RESET_APE 24
#define TEGRA210_MC_RESET_SE 25
#define TEGRA210_MC_RESET_NVJPG 26
#define TEGRA210_MC_RESET_AXIAP 27
#define TEGRA210_MC_RESET_ETR 28
#define TEGRA210_MC_RESET_TSECB 29
#endif

19
include/dt-bindings/memory/tegra30-mc.h
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@@ -22,4 +22,23 @@
#define TEGRA_SWGROUP_MPCORE 17
#define TEGRA_SWGROUP_ISP 18
#define TEGRA30_MC_RESET_AFI 0
#define TEGRA30_MC_RESET_AVPC 1
#define TEGRA30_MC_RESET_DC 2
#define TEGRA30_MC_RESET_DCB 3
#define TEGRA30_MC_RESET_EPP 4
#define TEGRA30_MC_RESET_2D 5
#define TEGRA30_MC_RESET_HC 6
#define TEGRA30_MC_RESET_HDA 7
#define TEGRA30_MC_RESET_ISP 8
#define TEGRA30_MC_RESET_MPCORE 9
#define TEGRA30_MC_RESET_MPCORELP 10
#define TEGRA30_MC_RESET_MPE 11
#define TEGRA30_MC_RESET_3D 12
#define TEGRA30_MC_RESET_3D2 13
#define TEGRA30_MC_RESET_PPCS 14
#define TEGRA30_MC_RESET_SATA 15
#define TEGRA30_MC_RESET_VDE 16
#define TEGRA30_MC_RESET_VI 17
#endif

21
include/dt-bindings/net/microchip-lan78xx.h Normal file
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@@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H
#define _DT_BINDINGS_MICROCHIP_LAN78XX_H
/* LED modes for LAN7800/LAN7850 embedded PHY */
#define LAN78XX_LINK_ACTIVITY 0
#define LAN78XX_LINK_1000_ACTIVITY 1
#define LAN78XX_LINK_100_ACTIVITY 2
#define LAN78XX_LINK_10_ACTIVITY 3
#define LAN78XX_LINK_100_1000_ACTIVITY 4
#define LAN78XX_LINK_10_1000_ACTIVITY 5
#define LAN78XX_LINK_10_100_ACTIVITY 6
#define LAN78XX_DUPLEX_COLLISION 8
#define LAN78XX_COLLISION 9
#define LAN78XX_ACTIVITY 10
#define LAN78XX_AUTONEG_FAULT 12
#define LAN78XX_FORCE_LED_OFF 14
#define LAN78XX_FORCE_LED_ON 15
#endif

37
include/dt-bindings/phy/phy-qcom-qusb2.h Normal file
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@@ -0,0 +1,37 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_
#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_
/* PHY HSTX TRIM bit values (24mA to 15mA) */
#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0
#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1
#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2
#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3
#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4
#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5
#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6
#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7
#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8
#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9
#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa
#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb
#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc
#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd
#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe
#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf
/* PHY PREEMPHASIS bit values */
#define QUSB2_V2_PREEMPHASIS_NONE 0
#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1
#define QUSB2_V2_PREEMPHASIS_10_PERCENT 2
#define QUSB2_V2_PREEMPHASIS_15_PERCENT 3
/* PHY PREEMPHASIS-WIDTH bit values */
#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT 0
#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT 1
#endif

90
include/dt-bindings/pinctrl/mt7623-pinfunc.h
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@@ -23,20 +23,26 @@
#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
#define MT7623_PIN_7_SPI1_CSN_FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
#define MT7623_PIN_8_SPI1_MI_FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
#define MT7623_PIN_9_SPI1_MO_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
#define MT7623_PIN_9_SPI1_MO_FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
@@ -53,6 +59,7 @@
#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1)
#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
#define MT7623_PIN_14_GPIO14_FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
@@ -60,88 +67,139 @@
#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
#define MT7623_PIN_18_PCM_CLK_FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
#define MT7623_PIN_18_PCM_CLK_FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
#define MT7623_PIN_18_PCM_CLK_FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6)
#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
#define MT7623_PIN_19_PCM_SYNC_FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
#define MT7623_PIN_19_PCM_SYNC_FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6)
#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
#define MT7623_PIN_20_PCM_RX_FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
#define MT7623_PIN_20_PCM_RX_FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
#define MT7623_PIN_20_PCM_RX_FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6)
#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
#define MT7623_PIN_21_PCM_TX_FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
#define MT7623_PIN_21_PCM_TX_FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
#define MT7623_PIN_21_PCM_TX_FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6)
#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2)
#define MT7623_PIN_22_EINT0_FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
#define MT7623_PIN_22_EINT0_FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
#define MT7623_PIN_22_EINT0_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1)
#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2)
#define MT7623_PIN_23_EINT1_FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
#define MT7623_PIN_23_EINT1_FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
#define MT7623_PIN_23_EINT1_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2)
#define MT7623_PIN_24_EINT2_FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
#define MT7623_PIN_24_EINT2_FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1)
#define MT7623_PIN_25_EINT3_FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
#define MT7623_PIN_25_EINT3_FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
#define MT7623_PIN_26_EINT4_FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
#define MT7623_PIN_26_EINT4_FUNC_KROW3 (MTK_PIN_NO(26) | 3)
#define MT7623_PIN_26_EINT4_FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
#define MT7623_PIN_26_EINT4_FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1)
#define MT7623_PIN_27_EINT5_FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
#define MT7623_PIN_27_EINT5_FUNC_KROW2 (MTK_PIN_NO(27) | 3)
#define MT7623_PIN_27_EINT5_FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
#define MT7623_PIN_28_EINT6_FUNC_KROW1 (MTK_PIN_NO(28) | 3)
#define MT7623_PIN_28_EINT6_FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1)
#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
#define MT7623_PIN_29_EINT7_FUNC_KROW0 (MTK_PIN_NO(29) | 3)
#define MT7623_PIN_29_EINT7_FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
#define MT7623_PIN_29_EINT7_FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6)
#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
#define MT7623_PIN_33_I2S1_DATA_FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
#define MT7623_PIN_33_I2S1_DATA_FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6)
#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
#define MT7623_PIN_35_I2S1_BCK_FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6)
#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
#define MT7623_PIN_37_I2S1_MCLK_FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1)
#define MT7623_PIN_39_JTMS_FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
#define MT7623_PIN_39_JTMS_FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
#define MT7623_PIN_39_JTMS_FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1)
#define MT7623_PIN_40_JTCK_FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
#define MT7623_PIN_40_JTCK_FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
#define MT7623_PIN_40_JTCK_FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1)
#define MT7623_PIN_41_JTDI_FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
#define MT7623_PIN_41_JTDI_FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1)
#define MT7623_PIN_42_JTDO_FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
#define MT7623_PIN_42_JTDO_FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1)
@@ -160,31 +218,40 @@
#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1)
#define MT7623_PIN_47_NREB_FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1)
#define MT7623_PIN_48_NRNB_FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6)
#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
#define MT7623_PIN_53_SPI0_CSN_FUNC_SPDIF (MTK_PIN_NO(53) | 3)
#define MT7623_PIN_53_SPI0_CSN_FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5)
#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
#define MT7623_PIN_54_SPI0_CK_FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
#define MT7623_PIN_54_SPI0_CK_FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
#define MT7623_PIN_55_SPI0_MI_FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5)
#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
#define MT7623_PIN_56_SPI0_MO_FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
#define MT7623_PIN_57_SDA1_FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT7623_PIN_57_SDA1_FUNC_SDA1 (MTK_PIN_NO(57) | 1)
@@ -275,10 +342,23 @@
#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
#define MT7623_PIN_83_LCM_RST_FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1)
#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1)
#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1)
#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1)
#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1)
@@ -300,20 +380,24 @@
#define MT7623_PIN_101_SPI2_CSN_FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
#define MT7623_PIN_101_SPI2_CSN_FUNC_SCL3 (MTK_PIN_NO(101) | 3)
#define MT7623_PIN_101_SPI2_CSN_FUNC_KROW0 (MTK_PIN_NO(101) | 4)
#define MT7623_PIN_102_SPI2_MI_FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
#define MT7623_PIN_102_SPI2_MI_FUNC_SDA3 (MTK_PIN_NO(102) | 3)
#define MT7623_PIN_102_SPI2_MI_FUNC_KROW1 (MTK_PIN_NO(102) | 4)
#define MT7623_PIN_103_SPI2_MO_FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
#define MT7623_PIN_103_SPI2_MO_FUNC_SCL3 (MTK_PIN_NO(103) | 3)
#define MT7623_PIN_103_SPI2_MO_FUNC_KROW2 (MTK_PIN_NO(103) | 4)
#define MT7623_PIN_104_SPI2_CK_FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
#define MT7623_PIN_104_SPI2_CK_FUNC_SDA3 (MTK_PIN_NO(104) | 3)
#define MT7623_PIN_104_SPI2_CK_FUNC_KROW3 (MTK_PIN_NO(104) | 4)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
@@ -394,7 +478,7 @@
#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT7623_PIN_122_GPIO122_FUNC_TEST (MTK_PIN_NO(122) | 1)
#define MT7623_PIN_122_GPIO122_FUNC_CEC (MTK_PIN_NO(122) | 1)
#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
@@ -404,12 +488,12 @@
#define MT7623_PIN_123_HTPLG_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)
#define MT7623_PIN_124_GPIO124_FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4)
#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5)
#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
#define MT7623_PIN_125_GPIO125_FUNC_TEST (MTK_PIN_NO(125) | 1)
#define MT7623_PIN_125_GPIO125_FUNC_HDMISD (MTK_PIN_NO(125) | 1)
#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4)
#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5)

27
include/dt-bindings/power/px30-power.h Normal file
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@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__
#define __DT_BINDINGS_POWER_PX30_POWER_H__
/* VD_CORE */
#define PX30_PD_A35_0 0
#define PX30_PD_A35_1 1
#define PX30_PD_A35_2 2
#define PX30_PD_A35_3 3
#define PX30_PD_SCU 4
/* VD_LOGIC */
#define PX30_PD_USB 5
#define PX30_PD_DDR 6
#define PX30_PD_SDCARD 7
#define PX30_PD_CRYPTO 8
#define PX30_PD_GMAC 9
#define PX30_PD_MMC_NAND 10
#define PX30_PD_VPU 11
#define PX30_PD_VO 12
#define PX30_PD_VI 13
#define PX30_PD_GPU 14
/* VD_PMU */
#define PX30_PD_PMU 15
#endif

22
include/dt-bindings/power/r8a77470-sysc.h Normal file
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@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A77470_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77470_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77470_PD_CA7_CPU0 5
#define R8A77470_PD_CA7_CPU1 6
#define R8A77470_PD_SGX 20
#define R8A77470_PD_CA7_SCU 21
/* Always-on power area */
#define R8A77470_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77470_SYSC_H__ */

26
include/dt-bindings/power/r8a77990-sysc.h Normal file
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@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77990_PD_CA53_CPU0 5
#define R8A77990_PD_CA53_CPU1 6
#define R8A77990_PD_CR7 13
#define R8A77990_PD_A3VC 14
#define R8A77990_PD_3DG_A 17
#define R8A77990_PD_3DG_B 18
#define R8A77990_PD_CA53_SCU 21
#define R8A77990_PD_A2VC1 26
/* Always-on power area */
#define R8A77990_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */

13
include/dt-bindings/power/rk3036-power.h Normal file
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@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RK3036_POWER_H__
#define __DT_BINDINGS_POWER_RK3036_POWER_H__
#define RK3036_PD_MSCH 0
#define RK3036_PD_CORE 1
#define RK3036_PD_PERI 2
#define RK3036_PD_VIO 3
#define RK3036_PD_VPU 4
#define RK3036_PD_GPU 5
#define RK3036_PD_SYS 6
#endif

14
include/dt-bindings/power/rk3128-power.h Normal file
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@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RK3128_POWER_H__
#define __DT_BINDINGS_POWER_RK3128_POWER_H__
/* VD_CORE */
#define RK3128_PD_CORE 0
/* VD_LOGIC */
#define RK3128_PD_VIO 1
#define RK3128_PD_VIDEO 2
#define RK3128_PD_GPU 3
#define RK3128_PD_MSCH 4
#endif

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