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[ARM] 3783/1: S3C2412: fix IRQ_EINT0 to IRQ_EINT3 handling

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Patch from Ben Dooks

The IRQ_EINT0 through IRQ_EINT3 handling has changed
on the S3C2412 from the previous SoCs in the range,
and thus we need to add code to handle this.

The changes come about due to these IRQs being
displayed in two different registers, and needing to
be acked and masked in both.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks
2006-09-09 21:24:13 +01:00
committed by Russell King
parent 3c06cd1c99
commit c6e58ebb37
4 changed files with 138 additions and 2 deletions
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4
arch/arm/mach-s3c2410/irq.c
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@@ -86,7 +86,7 @@ unsigned long s3c_irqwake_intmask = 0xffffffffL;
unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
unsigned long s3c_irqwake_eintmask = 0xffffffffL;
static int
int
s3c_irq_wake(unsigned int irqno, unsigned int state)
{
unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
@@ -260,7 +260,7 @@ s3c_irqext_unmask(unsigned int irqno)
s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
}
static int
int
s3c_irqext_type(unsigned int irq, unsigned int type)
{
void __iomem *extint_reg;