USB: musb: add Blackfin specific configuration to MUSB
Some config registers are not avaiable in Blackfin, we have to comment them out. v1-v2: - remove Blackfin specific header file - add Blackfin register version to musb_regs.h header file Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Tento commit je obsažen v:
Bryan Wu
@@ -37,97 +37,6 @@
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#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
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/*
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* Common USB registers
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*/
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#define MUSB_FADDR 0x00 /* 8-bit */
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#define MUSB_POWER 0x01 /* 8-bit */
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#define MUSB_INTRTX 0x02 /* 16-bit */
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#define MUSB_INTRRX 0x04
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#define MUSB_INTRTXE 0x06
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#define MUSB_INTRRXE 0x08
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#define MUSB_INTRUSB 0x0A /* 8 bit */
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#define MUSB_INTRUSBE 0x0B /* 8 bit */
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#define MUSB_FRAME 0x0C
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#define MUSB_INDEX 0x0E /* 8 bit */
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#define MUSB_TESTMODE 0x0F /* 8 bit */
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/* Get offset for a given FIFO from musb->mregs */
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#ifdef CONFIG_USB_TUSB6010
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#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
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#else
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#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
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#endif
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/*
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* Additional Control Registers
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*/
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#define MUSB_DEVCTL 0x60 /* 8 bit */
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/* These are always controlled through the INDEX register */
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#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
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#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
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#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
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#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
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/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
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#define MUSB_HWVERS 0x6C /* 8 bit */
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#define MUSB_EPINFO 0x78 /* 8 bit */
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#define MUSB_RAMINFO 0x79 /* 8 bit */
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#define MUSB_LINKINFO 0x7a /* 8 bit */
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#define MUSB_VPLEN 0x7b /* 8 bit */
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#define MUSB_HS_EOF1 0x7c /* 8 bit */
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#define MUSB_FS_EOF1 0x7d /* 8 bit */
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#define MUSB_LS_EOF1 0x7e /* 8 bit */
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/* Offsets to endpoint registers */
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#define MUSB_TXMAXP 0x00
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#define MUSB_TXCSR 0x02
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#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
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#define MUSB_RXMAXP 0x04
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#define MUSB_RXCSR 0x06
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#define MUSB_RXCOUNT 0x08
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#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
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#define MUSB_TXTYPE 0x0A
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#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
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#define MUSB_TXINTERVAL 0x0B
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#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
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#define MUSB_RXTYPE 0x0C
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#define MUSB_RXINTERVAL 0x0D
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#define MUSB_FIFOSIZE 0x0F
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#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
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/* Offsets to endpoint registers in indexed model (using INDEX register) */
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#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
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(0x10 + (_offset))
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/* Offsets to endpoint registers in flat models */
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#define MUSB_FLAT_OFFSET(_epnum, _offset) \
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(0x100 + (0x10*(_epnum)) + (_offset))
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#ifdef CONFIG_USB_TUSB6010
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/* TUSB6010 EP0 configuration register is special */
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#define MUSB_TUSB_OFFSET(_epnum, _offset) \
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(0x10 + _offset)
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#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
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#endif
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/* "bus control"/target registers, for host side multipoint (external hubs) */
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#define MUSB_TXFUNCADDR 0x00
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#define MUSB_TXHUBADDR 0x02
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#define MUSB_TXHUBPORT 0x03
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#define MUSB_RXFUNCADDR 0x04
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#define MUSB_RXHUBADDR 0x06
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#define MUSB_RXHUBPORT 0x07
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#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
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(0x80 + (8*(_epnum)) + (_offset))
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/*
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* MUSB Register bits
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*/
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@@ -228,7 +137,6 @@
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/* TXCSR in Peripheral and Host mode */
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#define MUSB_TXCSR_AUTOSET 0x8000
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#define MUSB_TXCSR_MODE 0x2000
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#define MUSB_TXCSR_DMAENAB 0x1000
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#define MUSB_TXCSR_FRCDATATOG 0x0800
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#define MUSB_TXCSR_DMAMODE 0x0400
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@@ -297,4 +205,309 @@
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/* HUBADDR */
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#define MUSB_HUBADDR_MULTI_TT 0x80
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#ifndef CONFIG_BLACKFIN
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/*
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* Common USB registers
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*/
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#define MUSB_FADDR 0x00 /* 8-bit */
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#define MUSB_POWER 0x01 /* 8-bit */
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#define MUSB_INTRTX 0x02 /* 16-bit */
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#define MUSB_INTRRX 0x04
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#define MUSB_INTRTXE 0x06
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#define MUSB_INTRRXE 0x08
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#define MUSB_INTRUSB 0x0A /* 8 bit */
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#define MUSB_INTRUSBE 0x0B /* 8 bit */
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#define MUSB_FRAME 0x0C
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#define MUSB_INDEX 0x0E /* 8 bit */
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#define MUSB_TESTMODE 0x0F /* 8 bit */
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/* Get offset for a given FIFO from musb->mregs */
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#ifdef CONFIG_USB_TUSB6010
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#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
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#else
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#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
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#endif
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/*
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* Additional Control Registers
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*/
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#define MUSB_DEVCTL 0x60 /* 8 bit */
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/* These are always controlled through the INDEX register */
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#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
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#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
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#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
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#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
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/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
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#define MUSB_HWVERS 0x6C /* 8 bit */
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#define MUSB_EPINFO 0x78 /* 8 bit */
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#define MUSB_RAMINFO 0x79 /* 8 bit */
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#define MUSB_LINKINFO 0x7a /* 8 bit */
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#define MUSB_VPLEN 0x7b /* 8 bit */
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#define MUSB_HS_EOF1 0x7c /* 8 bit */
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#define MUSB_FS_EOF1 0x7d /* 8 bit */
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#define MUSB_LS_EOF1 0x7e /* 8 bit */
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/* Offsets to endpoint registers */
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#define MUSB_TXMAXP 0x00
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#define MUSB_TXCSR 0x02
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#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
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#define MUSB_RXMAXP 0x04
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#define MUSB_RXCSR 0x06
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#define MUSB_RXCOUNT 0x08
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#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
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#define MUSB_TXTYPE 0x0A
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#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
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#define MUSB_TXINTERVAL 0x0B
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#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
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#define MUSB_RXTYPE 0x0C
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#define MUSB_RXINTERVAL 0x0D
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#define MUSB_FIFOSIZE 0x0F
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#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
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/* Offsets to endpoint registers in indexed model (using INDEX register) */
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#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
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(0x10 + (_offset))
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/* Offsets to endpoint registers in flat models */
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#define MUSB_FLAT_OFFSET(_epnum, _offset) \
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(0x100 + (0x10*(_epnum)) + (_offset))
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#ifdef CONFIG_USB_TUSB6010
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/* TUSB6010 EP0 configuration register is special */
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#define MUSB_TUSB_OFFSET(_epnum, _offset) \
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(0x10 + _offset)
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#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
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#endif
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#define MUSB_TXCSR_MODE 0x2000
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/* "bus control"/target registers, for host side multipoint (external hubs) */
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#define MUSB_TXFUNCADDR 0x00
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#define MUSB_TXHUBADDR 0x02
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#define MUSB_TXHUBPORT 0x03
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#define MUSB_RXFUNCADDR 0x04
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#define MUSB_RXHUBADDR 0x06
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#define MUSB_RXHUBPORT 0x07
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#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
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(0x80 + (8*(_epnum)) + (_offset))
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static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
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{
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musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
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}
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static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
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{
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musb_writew(mbase, MUSB_TXFIFOADD, c_off);
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}
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static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
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{
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musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
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}
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static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
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{
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musb_writew(mbase, MUSB_RXFIFOADD, c_off);
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}
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static inline u8 musb_read_configdata(void __iomem *mbase)
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{
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return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
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}
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static inline u16 musb_read_hwvers(void __iomem *mbase)
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{
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return musb_readw(mbase, MUSB_HWVERS);
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}
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static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
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{
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return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
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}
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static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
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u8 qh_addr_reg)
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{
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musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
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}
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static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
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u8 qh_h_addr_reg)
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{
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musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
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}
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static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
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u8 qh_h_port_reg)
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{
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musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
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}
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static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
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u8 qh_addr_reg)
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{
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musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
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qh_addr_reg);
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}
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static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
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u8 qh_addr_reg)
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{
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musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
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qh_addr_reg);
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}
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static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
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u8 qh_h_port_reg)
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{
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musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
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qh_h_port_reg);
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}
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#else /* CONFIG_BLACKFIN */
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#define USB_BASE USB_FADDR
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#define USB_OFFSET(reg) (reg - USB_BASE)
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/*
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* Common USB registers
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*/
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#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
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#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
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#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
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#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
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#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
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#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
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#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
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#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
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#define MUSB_FRAME USB_OFFSET(USB_FRAME)
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#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
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#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
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/* Get offset for a given FIFO from musb->mregs */
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#define MUSB_FIFO_OFFSET(epnum) \
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(USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
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/*
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* Additional Control Registers
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*/
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#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
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#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
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#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
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#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
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#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
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#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
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/* Offsets to endpoint registers */
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#define MUSB_TXMAXP 0x00
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#define MUSB_TXCSR 0x04
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#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
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#define MUSB_RXMAXP 0x08
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#define MUSB_RXCSR 0x0C
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#define MUSB_RXCOUNT 0x10
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#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
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#define MUSB_TXTYPE 0x14
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#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
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#define MUSB_TXINTERVAL 0x18
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#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
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#define MUSB_RXTYPE 0x1C
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#define MUSB_RXINTERVAL 0x20
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#define MUSB_TXCOUNT 0x28
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/* Offsets to endpoint registers in indexed model (using INDEX register) */
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#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
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(0x40 + (_offset))
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/* Offsets to endpoint registers in flat models */
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#define MUSB_FLAT_OFFSET(_epnum, _offset) \
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(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
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/* Not implemented - HW has seperate Tx/Rx FIFO */
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#define MUSB_TXCSR_MODE 0x0000
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/*
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* Dummy stub for clk framework, it will be removed
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* until Blackfin supports clk framework
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*/
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#define clk_get(dev, id) NULL
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#define clk_put(clock) do {} while (0)
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#define clk_enable(clock) do {} while (0)
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#define clk_disable(clock) do {} while (0)
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static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
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{
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}
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static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
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{
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}
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static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
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{
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}
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static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
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{
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}
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static inline u8 musb_read_configdata(void __iomem *mbase)
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{
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return 0;
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}
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static inline u16 musb_read_hwvers(void __iomem *mbase)
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{
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return 0;
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}
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static inline u16 musb_read_target_reg_base(u8 i, void __iomem *mbase)
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{
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return 0;
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}
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static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
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u8 qh_addr_req)
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{
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}
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static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
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u8 qh_h_addr_reg)
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{
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}
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static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
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u8 qh_h_port_reg)
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{
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}
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static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
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u8 qh_addr_reg)
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{
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}
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static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
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u8 qh_addr_reg)
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{
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}
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static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
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u8 qh_h_port_reg)
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{
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}
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#endif /* CONFIG_BLACKFIN */
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#endif /* __MUSB_REGS_H__ */
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