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aacraid: Enable 64bit write to controller register

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If writeq() not supported, then do atomic two 32bit write

Reviewed-by: Tomas Henzl <thenzl@redhat.com>
Reviewed-by: Murthy Bhat <Murthy.Bhat@pmcs.com>
Reviewed-by: Karthikeya Sunkesula <Karthikeya.Sunkesula@pmcs.com>
Signed-off-by: Mahesh Rajashekhara <Mahesh.Rajashekhara@pmcs.com>
Signed-off-by: James Bottomley <JBottomley@Odin.com>
This commit is contained in:
Mahesh Rajashekhara
2015-08-28 06:38:36 -04:00
committed by James Bottomley
parent 9022d375bd
commit c6992781d9
3 changed files with 20 additions and 2 deletions
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9
drivers/scsi/aacraid/aacraid.h
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@@ -844,6 +844,10 @@ struct src_registers {
&((AEP)->regs.src.bar0->CSR))
#define src_writel(AEP, CSR, value) writel(value, \
&((AEP)->regs.src.bar0->CSR))
#if defined(writeq)
#define src_writeq(AEP, CSR, value) writeq(value, \
&((AEP)->regs.src.bar0->CSR))
#endif
#define SRC_ODR_SHIFT 12
#define SRC_IDR_SHIFT 9
@@ -1163,6 +1167,11 @@ struct aac_dev
struct fsa_dev_info *fsa_dev;
struct task_struct *thread;
int cardtype;
/*
*This lock will protect the two 32-bit
*writes to the Inbound Queue
*/
spinlock_t iq_lock;
/*
* The following is the device specific extension.