gpio: move mpc8xxx/512x gpio driver to drivers/gpio
Move the driver to the place where it is expected to be nowadays. Also rename its CONFIG-name to match the rest and adapt the defconfigs. Finally, move selection of REQUIRE_GPIOLIB or WANTS_OPTIONAL_GPIOLIB to the platforms, because this option is per-platform and not per-driver. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Wolfram Sang
committed by
Anatolij Gustschin
Anatolij Gustschin
parent
40dc7e8b4a
commit
c68308dd50
@@ -18,7 +18,6 @@ obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
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obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
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obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
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obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
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obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
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obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
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obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
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obj-$(CONFIG_FSL_RIO) += fsl_rio.o
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@@ -1,395 +0,0 @@
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/*
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* GPIOs on MPC512x/8349/8572/8610 and compatible
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*
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* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#define MPC8XXX_GPIO_PINS 32
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#define GPIO_DIR 0x00
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#define GPIO_ODR 0x04
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#define GPIO_DAT 0x08
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#define GPIO_IER 0x0c
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#define GPIO_IMR 0x10
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#define GPIO_ICR 0x14
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#define GPIO_ICR2 0x18
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struct mpc8xxx_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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/*
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* shadowed data register to be able to clear/set output pins in
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* open drain mode safely
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*/
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u32 data;
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struct irq_host *irq;
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void *of_dev_id_data;
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};
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static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
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{
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return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
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}
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static inline struct mpc8xxx_gpio_chip *
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to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
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{
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return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
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}
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static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
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}
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/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
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* defined as output cannot be determined by reading GPDAT register,
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* so we use shadow data register instead. The status of input pins
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* is determined by reading GPDAT register.
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*/
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static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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u32 val;
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
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return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
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}
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static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
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}
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static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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if (val)
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mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
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else
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mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
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out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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return 0;
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}
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static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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unsigned long flags;
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mpc8xxx_gpio_set(gc, gpio, val);
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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return 0;
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}
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static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
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return irq_create_mapping(mpc8xxx_gc->irq, offset);
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else
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return -ENXIO;
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}
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static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned int mask;
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mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
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if (mask)
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generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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32 - ffs(mask)));
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}
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static void mpc8xxx_irq_unmask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_mask(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_ack(struct irq_data *d)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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}
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static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long gpio = irqd_to_hwirq(d);
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void __iomem *reg;
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unsigned int shift;
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unsigned long flags;
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if (gpio < 16) {
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reg = mm->regs + GPIO_ICR;
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shift = (15 - gpio) * 2;
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} else {
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reg = mm->regs + GPIO_ICR2;
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shift = (15 - (gpio % 16)) * 2;
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}
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrsetbits_be32(reg, 3 << shift, 2 << shift);
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrsetbits_be32(reg, 3 << shift, 1 << shift);
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(reg, 3 << shift);
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct irq_chip mpc8xxx_irq_chip = {
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.name = "mpc8xxx-gpio",
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.irq_unmask = mpc8xxx_irq_unmask,
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.irq_mask = mpc8xxx_irq_mask,
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.irq_ack = mpc8xxx_irq_ack,
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.irq_set_type = mpc8xxx_irq_set_type,
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};
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static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
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if (mpc8xxx_gc->of_dev_id_data)
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mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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/* interrupt sense values coming from the device tree equal either
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* EDGE_FALLING or EDGE_BOTH
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*/
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*out_hwirq = intspec[0];
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*out_flags = intspec[1];
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return 0;
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}
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static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
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.map = mpc8xxx_gpio_irq_map,
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.xlate = mpc8xxx_gpio_irq_xlate,
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};
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static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
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{ .compatible = "fsl,mpc8349-gpio", },
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{ .compatible = "fsl,mpc8572-gpio", },
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{ .compatible = "fsl,mpc8610-gpio", },
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{ .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
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{ .compatible = "fsl,qoriq-gpio", },
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{}
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};
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static void __init mpc8xxx_add_controller(struct device_node *np)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct gpio_chip *gc;
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const struct of_device_id *id;
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unsigned hwirq;
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int ret;
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mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
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if (!mpc8xxx_gc) {
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ret = -ENOMEM;
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goto err;
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}
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spin_lock_init(&mpc8xxx_gc->lock);
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mm_gc = &mpc8xxx_gc->mm_gc;
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gc = &mm_gc->gc;
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mm_gc->save_regs = mpc8xxx_gpio_save_regs;
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gc->ngpio = MPC8XXX_GPIO_PINS;
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gc->direction_input = mpc8xxx_gpio_dir_in;
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gc->direction_output = mpc8xxx_gpio_dir_out;
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if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
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gc->get = mpc8572_gpio_get;
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else
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gc->get = mpc8xxx_gpio_get;
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gc->set = mpc8xxx_gpio_set;
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gc->to_irq = mpc8xxx_gpio_to_irq;
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ret = of_mm_gpiochip_add(np, mm_gc);
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if (ret)
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goto err;
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hwirq = irq_of_parse_and_map(np, 0);
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if (hwirq == NO_IRQ)
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goto skip_irq;
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mpc8xxx_gc->irq =
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irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
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&mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
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if (!mpc8xxx_gc->irq)
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goto skip_irq;
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id = of_match_node(mpc8xxx_gpio_ids, np);
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if (id)
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mpc8xxx_gc->of_dev_id_data = id->data;
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mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
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/* ack and mask all irqs */
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out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
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out_be32(mm_gc->regs + GPIO_IMR, 0);
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irq_set_handler_data(hwirq, mpc8xxx_gc);
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irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
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skip_irq:
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return;
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err:
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pr_err("%s: registration failed with status %d\n",
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np->full_name, ret);
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kfree(mpc8xxx_gc);
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return;
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}
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static int __init mpc8xxx_add_gpiochips(void)
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{
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struct device_node *np;
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for_each_matching_node(np, mpc8xxx_gpio_ids)
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mpc8xxx_add_controller(np);
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return 0;
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}
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arch_initcall(mpc8xxx_add_gpiochips);
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