Merge tag 'iio-fixes-for-4.16a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-linus
Jonathan writes: First round of IIO fixes for the 4.16 cycle. One nasty very old crash around polling for buffers that aren't there - though that can only cause effects on drivers that support events but not buffers. * buffer / kfifo handling in the core. - Check there is a buffer and return 0 from poll directly if there isn't. Poll doesn't make sense in this circumstances, but best to close the hole. * ad5933 - Change the marked buffer mode to a software buffer as the meaning of the hardware buffer label has long since changed and this uses a front end software buffer anyway. * ad7192 - Fix the fact the external clock frequency was only set when using the internal clock which was less than helpful. * adis_lib - Initialize the trigger before requesting the interrupt. Some newer parts can power up with interrupt generation enabled so ordering now matters. * aspeed-adc - Fix an errror handling path as labels and general ordering were wrong. * srf08 - Fix a link error due to undefined devm_iio_triggered_buffer_setup. * stm32-adc - Fix error handling unwind squence in stm32h7_adc_enable.
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@@ -243,7 +243,7 @@ static int aspeed_adc_probe(struct platform_device *pdev)
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ASPEED_ADC_INIT_POLLING_TIME,
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ASPEED_ADC_INIT_TIMEOUT);
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if (ret)
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goto scaler_error;
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goto poll_timeout_error;
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}
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/* Start all channels in normal mode. */
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@@ -274,9 +274,10 @@ iio_register_error:
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writel(ASPEED_OPERATION_MODE_POWER_DOWN,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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clk_disable_unprepare(data->clk_scaler->clk);
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reset_error:
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reset_control_assert(data->rst);
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clk_enable_error:
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poll_timeout_error:
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reset_control_assert(data->rst);
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reset_error:
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clk_hw_unregister_divider(data->clk_scaler);
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scaler_error:
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clk_hw_unregister_divider(data->clk_prescaler);
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@@ -722,8 +722,6 @@ static int stm32h7_adc_enable(struct stm32_adc *adc)
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int ret;
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u32 val;
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/* Clear ADRDY by writing one, then enable ADC */
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stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
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stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
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/* Poll for ADRDY to be set (after adc startup time) */
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@@ -731,8 +729,11 @@ static int stm32h7_adc_enable(struct stm32_adc *adc)
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val & STM32H7_ADRDY,
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100, STM32_ADC_TIMEOUT_US);
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if (ret) {
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stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
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stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
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dev_err(&indio_dev->dev, "Failed to enable ADC\n");
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} else {
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/* Clear ADRDY by writing one */
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stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
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}
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return ret;
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