Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon: "Mostly just incremental improvements here: - Introduce AT_HWCAP2 for advertising CPU features to userspace - Expose SVE2 availability to userspace - Support for "data cache clean to point of deep persistence" (DC PODP) - Honour "mitigations=off" on the cmdline and advertise status via sysfs - CPU timer erratum workaround (Neoverse-N1 #1188873) - Introduce perf PMU driver for the SMMUv3 performance counters - Add config option to disable the kuser helpers page for AArch32 tasks - Futex modifications to ensure liveness under contention - Rework debug exception handling to seperate kernel and user handlers - Non-critical fixes and cleanup" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (92 commits) Documentation: Add ARM64 to kernel-parameters.rst arm64/speculation: Support 'mitigations=' cmdline option arm64: ssbs: Don't treat CPUs with SSBS as unaffected by SSB arm64: enable generic CPU vulnerabilites support arm64: add sysfs vulnerability show for speculative store bypass arm64: Fix size of __early_cpu_boot_status clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters clocksource/arm_arch_timer: Remove use of workaround static key clocksource/arm_arch_timer: Drop use of static key in arch_timer_reg_read_stable clocksource/arm_arch_timer: Direcly assign set_next_event workaround arm64: Use arch_timer_read_counter instead of arch_counter_get_cntvct watchdog/sbsa: Use arch_timer_read_counter instead of arch_counter_get_cntvct ARM: vdso: Remove dependency with the arch_timer driver internals arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1 arm64: Add part number for Neoverse N1 arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT arm64: Restrict ARM64_ERRATUM_1188873 mitigation to AArch32 arm64: mm: Remove pte_unmap_nested() arm64: Fix compiler warning from pte_unmap() with -Wunused-but-set-variable arm64: compat: Reduce address limit for 64K pages ...
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@@ -11,6 +11,10 @@
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#include <clocksource/arm_arch_timer.h>
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#ifdef CONFIG_ARM_ARCH_TIMER
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/* 32bit ARM doesn't know anything about timer errata... */
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#define has_erratum_handler(h) (false)
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#define erratum_handler(h) (arch_timer_##h)
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int arch_timer_arch_init(void);
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/*
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@@ -79,7 +83,7 @@ static inline u32 arch_timer_get_cntfrq(void)
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return val;
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}
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static inline u64 arch_counter_get_cntpct(void)
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static inline u64 __arch_counter_get_cntpct(void)
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{
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u64 cval;
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@@ -88,7 +92,12 @@ static inline u64 arch_counter_get_cntpct(void)
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return cval;
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}
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static inline u64 arch_counter_get_cntvct(void)
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static inline u64 __arch_counter_get_cntpct_stable(void)
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{
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return __arch_counter_get_cntpct();
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}
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static inline u64 __arch_counter_get_cntvct(void)
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{
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u64 cval;
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@@ -97,6 +106,11 @@ static inline u64 arch_counter_get_cntvct(void)
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return cval;
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}
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static inline u64 __arch_counter_get_cntvct_stable(void)
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{
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return __arch_counter_get_cntvct();
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}
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static inline u32 arch_timer_get_cntkctl(void)
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{
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u32 cntkctl;
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@@ -68,6 +68,8 @@
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#define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
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#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
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#define CNTVCT __ACCESS_CP15_64(1, c14)
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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static inline unsigned long get_cr(void)
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@@ -32,14 +32,14 @@
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#define stage2_pgd_present(kvm, pgd) pgd_present(pgd)
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#define stage2_pgd_populate(kvm, pgd, pud) pgd_populate(NULL, pgd, pud)
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#define stage2_pud_offset(kvm, pgd, address) pud_offset(pgd, address)
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#define stage2_pud_free(kvm, pud) pud_free(NULL, pud)
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#define stage2_pud_free(kvm, pud) do { } while (0)
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#define stage2_pud_none(kvm, pud) pud_none(pud)
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#define stage2_pud_clear(kvm, pud) pud_clear(pud)
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#define stage2_pud_present(kvm, pud) pud_present(pud)
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#define stage2_pud_populate(kvm, pud, pmd) pud_populate(NULL, pud, pmd)
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#define stage2_pmd_offset(kvm, pud, address) pmd_offset(pud, address)
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#define stage2_pmd_free(kvm, pmd) pmd_free(NULL, pmd)
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#define stage2_pmd_free(kvm, pmd) free_page((unsigned long)pmd)
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#define stage2_pud_huge(kvm, pud) pud_huge(pud)
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