Merge tag 'xtensa-next-20130508' of git://github.com/czankel/xtensa-linux
Pull xtensa updates from Chris Zankel: "Support for the latest MMU architecture that allows for a larger accessible memory region, and various bug-fixes" * tag 'xtensa-next-20130508' of git://github.com/czankel/xtensa-linux: xtensa: Switch to asm-generic/linkage.h xtensa: fix redboot load address xtensa: ISS: fix timer_lock usage in rs_open xtensa: disable IRQs while IRQ handler is running xtensa: enable lockdep support xtensa: fix arch_irqs_disabled_flags implementation xtensa: add irq flags trace support xtensa: provide custom CALLER_ADDR* implementations xtensa: add stacktrace support xtensa: clean up stpill_registers xtensa: don't use a7 in simcalls xtensa: don't attempt to use unconfigured timers xtensa: provide default platform_pcibios_init implementation xtensa: remove KCORE_ELF again xtensa: document MMUv3 setup sequence xtensa: add MMU v3 support xtensa: fix ibreakenable register update xtensa: fix oprofile building as module
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@@ -24,15 +24,19 @@ void __init paging_init(void)
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*/
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void __init init_mmu(void)
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{
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/* Writing zeros to the <t>TLBCFG special registers ensure
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* that valid values exist in the register. For existing
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* PGSZID<w> fields, zero selects the first element of the
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* page-size array. For nonexistent PGSZID<w> fields, zero is
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* the best value to write. Also, when changing PGSZID<w>
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#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
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/*
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* Writing zeros to the instruction and data TLBCFG special
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* registers ensure that valid values exist in the register.
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*
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* For existing PGSZID<w> fields, zero selects the first element
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* of the page-size array. For nonexistent PGSZID<w> fields,
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* zero is the best value to write. Also, when changing PGSZID<w>
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* fields, the corresponding TLB must be flushed.
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*/
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set_itlbcfg_register(0);
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set_dtlbcfg_register(0);
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#endif
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flush_tlb_all();
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/* Set rasid register to a known value. */
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