Merge branch 'topic/bxt-stage1' into drm-intel-next-queued
Separate topic branch for bxt didn't work out since we needed to refactor the gmbus code a bit to make it look decent. So backmerge. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Tento commit je obsažen v:
Daniel Vetter
@@ -4541,12 +4541,116 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
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i915_cache_sharing_get, i915_cache_sharing_set,
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"%llu\n");
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struct sseu_dev_status {
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unsigned int slice_total;
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unsigned int subslice_total;
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unsigned int subslice_per_slice;
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unsigned int eu_total;
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unsigned int eu_per_subslice;
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};
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static void cherryview_sseu_device_status(struct drm_device *dev,
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struct sseu_dev_status *stat)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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const int ss_max = 2;
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int ss;
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u32 sig1[ss_max], sig2[ss_max];
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sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
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sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
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sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
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sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
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for (ss = 0; ss < ss_max; ss++) {
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unsigned int eu_cnt;
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if (sig1[ss] & CHV_SS_PG_ENABLE)
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/* skip disabled subslice */
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continue;
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stat->slice_total = 1;
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stat->subslice_per_slice++;
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eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
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((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
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((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
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((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
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stat->eu_total += eu_cnt;
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stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
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}
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stat->subslice_total = stat->subslice_per_slice;
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}
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static void gen9_sseu_device_status(struct drm_device *dev,
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struct sseu_dev_status *stat)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int s_max = 3, ss_max = 4;
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int s, ss;
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u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
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/* BXT has a single slice and at most 3 subslices. */
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if (IS_BROXTON(dev)) {
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s_max = 1;
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ss_max = 3;
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}
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for (s = 0; s < s_max; s++) {
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s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
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eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
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eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
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}
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eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
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GEN9_PGCTL_SSA_EU19_ACK |
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GEN9_PGCTL_SSA_EU210_ACK |
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GEN9_PGCTL_SSA_EU311_ACK;
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eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
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GEN9_PGCTL_SSB_EU19_ACK |
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GEN9_PGCTL_SSB_EU210_ACK |
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GEN9_PGCTL_SSB_EU311_ACK;
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for (s = 0; s < s_max; s++) {
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unsigned int ss_cnt = 0;
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if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
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/* skip disabled slice */
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continue;
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stat->slice_total++;
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if (IS_SKYLAKE(dev))
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ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
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for (ss = 0; ss < ss_max; ss++) {
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unsigned int eu_cnt;
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if (IS_BROXTON(dev) &&
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!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
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/* skip disabled subslice */
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continue;
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if (IS_BROXTON(dev))
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ss_cnt++;
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eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
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eu_mask[ss%2]);
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stat->eu_total += eu_cnt;
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stat->eu_per_subslice = max(stat->eu_per_subslice,
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eu_cnt);
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}
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stat->subslice_total += ss_cnt;
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stat->subslice_per_slice = max(stat->subslice_per_slice,
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ss_cnt);
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}
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}
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static int i915_sseu_status(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
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struct sseu_dev_status stat;
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if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
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return -ENODEV;
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@@ -4570,79 +4674,22 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
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yesno(INTEL_INFO(dev)->has_eu_pg));
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seq_puts(m, "SSEU Device Status\n");
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memset(&stat, 0, sizeof(stat));
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if (IS_CHERRYVIEW(dev)) {
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const int ss_max = 2;
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int ss;
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u32 sig1[ss_max], sig2[ss_max];
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sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
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sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
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sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
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sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
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for (ss = 0; ss < ss_max; ss++) {
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unsigned int eu_cnt;
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if (sig1[ss] & CHV_SS_PG_ENABLE)
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/* skip disabled subslice */
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continue;
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s_tot = 1;
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ss_per++;
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eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
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((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
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((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
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((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
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eu_tot += eu_cnt;
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eu_per = max(eu_per, eu_cnt);
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}
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ss_tot = ss_per;
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} else if (IS_SKYLAKE(dev)) {
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const int s_max = 3, ss_max = 4;
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int s, ss;
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u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
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s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
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s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
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s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
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eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
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eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
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eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
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eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
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eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
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eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
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eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
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GEN9_PGCTL_SSA_EU19_ACK |
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GEN9_PGCTL_SSA_EU210_ACK |
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GEN9_PGCTL_SSA_EU311_ACK;
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eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
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GEN9_PGCTL_SSB_EU19_ACK |
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GEN9_PGCTL_SSB_EU210_ACK |
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GEN9_PGCTL_SSB_EU311_ACK;
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for (s = 0; s < s_max; s++) {
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if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
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/* skip disabled slice */
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continue;
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s_tot++;
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ss_per = INTEL_INFO(dev)->subslice_per_slice;
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ss_tot += ss_per;
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for (ss = 0; ss < ss_max; ss++) {
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unsigned int eu_cnt;
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eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
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eu_mask[ss%2]);
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eu_tot += eu_cnt;
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eu_per = max(eu_per, eu_cnt);
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}
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}
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cherryview_sseu_device_status(dev, &stat);
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} else if (INTEL_INFO(dev)->gen >= 9) {
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gen9_sseu_device_status(dev, &stat);
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}
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seq_printf(m, " Enabled Slice Total: %u\n", s_tot);
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seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot);
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seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per);
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seq_printf(m, " Enabled EU Total: %u\n", eu_tot);
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seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per);
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seq_printf(m, " Enabled Slice Total: %u\n",
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stat.slice_total);
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seq_printf(m, " Enabled Subslice Total: %u\n",
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stat.subslice_total);
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seq_printf(m, " Enabled Subslice Per Slice: %u\n",
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stat.subslice_per_slice);
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seq_printf(m, " Enabled EU Total: %u\n",
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stat.eu_total);
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seq_printf(m, " Enabled EU Per Subslice: %u\n",
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stat.eu_per_subslice);
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return 0;
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}
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