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sh: sh7723 clock framework rewrite V2

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This patch contains V2 of the sh7723 clock framework
rewrite. The new code makes use of the recently merged
div4, div6 and mstp32 helper code. Both extal and dll
are supported as input clocks to the pll.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Esse commit está contido em:
Magnus Damm
2009-06-03 08:39:59 +00:00
commit de Paul Mundt
pai 098dee99d1
commit c521dc0203
4 arquivos alterados com 225 adições e 58 exclusões
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57
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
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@@ -1,7 +1,7 @@
/*
* arch/sh/kernel/cpu/sh4a/clock-sh7722.c
*
* SH7343, SH7722, SH7723 & SH7366 support for the clock framework
* SH7343, SH7722 & SH7366 support for the clock framework
*
* Copyright (c) 2006-2007 Nomad Global Solutions Inc
* Based on code for sh7343 by Paul Mundt
@@ -176,11 +176,6 @@ static unsigned long module_clk_recalc(struct clk *clk)
#define STCMASK 0x3f
#define DIVCALC(div) (div/2-1)
#define FRQCRKICK 0x80000000
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
#define MASTERDIVS { 6, 8, 12, 16 }
#define STCMASK 0x1f
#define DIVCALC(div) (div-1)
#define FRQCRKICK 0x00000000
#else
#define MASTERDIVS { 2, 3, 4, 6, 8, 16 }
#define STCMASK 0x1f
@@ -681,56 +676,6 @@ static struct clk sh7722_mstpcr_clocks[] = {
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7723)
/* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
MSTPCR("tlb0", "cpu_clk", 0, 31, 0),
MSTPCR("ic0", "cpu_clk", 0, 30, 0),
MSTPCR("oc0", "cpu_clk", 0, 29, 0),
MSTPCR("l2c0", "sh_clk", 0, 28, 0),
MSTPCR("ilmem0", "cpu_clk", 0, 27, 0),
MSTPCR("fpu0", "cpu_clk", 0, 24, 0),
MSTPCR("intc0", "cpu_clk", 0, 22, 0),
MSTPCR("dmac0", "bus_clk", 0, 21, 0),
MSTPCR("sh0", "sh_clk", 0, 20, 0),
MSTPCR("hudi0", "peripheral_clk", 0, 19, 0),
MSTPCR("ubc0", "cpu_clk", 0, 17, 0),
MSTPCR("tmu0", "peripheral_clk", 0, 15, 0),
MSTPCR("cmt0", "r_clk", 0, 14, 0),
MSTPCR("rwdt0", "r_clk", 0, 13, 0),
MSTPCR("dmac1", "bus_clk", 0, 12, 0),
MSTPCR("tmu1", "peripheral_clk", 0, 11, 0),
MSTPCR("flctl0", "peripheral_clk", 0, 10, 0),
MSTPCR("scif0", "peripheral_clk", 0, 9, 0),
MSTPCR("scif1", "peripheral_clk", 0, 8, 0),
MSTPCR("scif2", "peripheral_clk", 0, 7, 0),
MSTPCR("scif3", "bus_clk", 0, 6, 0),
MSTPCR("scif4", "bus_clk", 0, 5, 0),
MSTPCR("scif5", "bus_clk", 0, 4, 0),
MSTPCR("msiof0", "bus_clk", 0, 2, 0),
MSTPCR("msiof1", "bus_clk", 0, 1, 0),
MSTPCR("meram0", "sh_clk", 0, 0, CLK_ENABLE_ON_INIT),
MSTPCR("i2c0", "peripheral_clk", 1, 9, 0),
MSTPCR("rtc0", "r_clk", 1, 8, 0),
MSTPCR("atapi0", "sh_clk", 2, 28, 0),
MSTPCR("adc0", "peripheral_clk", 2, 28, 0),
MSTPCR("tpu0", "bus_clk", 2, 25, 0),
MSTPCR("irda0", "peripheral_clk", 2, 24, 0),
MSTPCR("tsif0", "bus_clk", 2, 22, 0),
MSTPCR("icb0", "bus_clk", 2, 21, 0),
MSTPCR("sdhi0", "bus_clk", 2, 18, 0),
MSTPCR("sdhi1", "bus_clk", 2, 17, 0),
MSTPCR("keysc0", "r_clk", 2, 14, 0),
MSTPCR("usb0", "bus_clk", 2, 11, 0),
MSTPCR("2dg0", "bus_clk", 2, 10, 0),
MSTPCR("siu0", "bus_clk", 2, 8, 0),
MSTPCR("veu1", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT),
MSTPCR("vou0", "bus_clk", 2, 5, 0),
MSTPCR("beu0", "bus_clk", 2, 4, 0),
MSTPCR("ceu0", "bus_clk", 2, 3, 0),
MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT),
MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT),
MSTPCR("lcdc0", "bus_clk", 2, 0, 0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7724)
/* See Datasheet : Overview -> Block Diagram */
MSTPCR("tlb0", "cpu_clk", 0, 31, 0),