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powerpc/8xx: Invalidate non present TLB as early as possible

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8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.

These must be invalidated separaly as linux mm doesn't.

Commit 5efab4a02c was invalidating them in
arch/powerpc/mm/fault.c.
This patch does the invalidation earlier in order to free the TLB as soon as
possible. This also has the advantage of removing some 8xx specific code from
fault.c

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
LEROY Christophe
2014-09-19 10:36:10 +02:00
committed by Scott Wood
parent 83c17ba35e
commit c51a6821bd
2 changed files with 10 additions and 12 deletions
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15
arch/powerpc/kernel/head_8xx.S
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@@ -475,8 +475,11 @@ InstructionTLBError1:
EXCEPTION_PROLOG_2
mr r4,r12
mr r5,r9
andis. r10,r5,0x4000
beq+ 1f
tlbie r4
/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
EXC_XFER_LITE(0x400, handle_page_fault)
1: EXC_XFER_LITE(0x400, handle_page_fault)
/* This is the data TLB error on the MPC8xx. This could be due to
* many reasons, including a dirty update to a pte. We bail out to
@@ -492,11 +495,13 @@ DataTLBError:
DARFixed:/* Return from dcbx instruction bug workaround */
EXCEPTION_PROLOG_1
EXCEPTION_PROLOG_2
mfspr r10,SPRN_DSISR
stw r10,_DSISR(r11)
mr r5,r10
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
mfspr r4,SPRN_DAR
li r10,RPN_PATTERN
andis. r10,r5,0x4000
beq+ 1f
tlbie r4
1: li r10,RPN_PATTERN
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
EXC_XFER_LITE(0x300, handle_page_fault)