Merge tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel into drm-next
- prep refactoring for execlists (Oscar Mateo) - corner-case fixes for runtime pm (Imre) - tons of vblank improvements from Ville - prep work for atomic plane/sprite updates (Ville) - more chv code, now almost complete (tons of different people) - refactoring and improvements for drm_irq.c merged through drm-intel-next - g4x/ilk reset improvements (Ville) - removal of encoder->mode_set - moved audio state tracking into pipe_config - shuffled fb pinning out of the platform crtc modeset callbacks into core code - userptr support (Chris) - OOM handling improvements from Chris, with now have a neat oom notifier which jumps additional debug information. - topdown allocation of ppgtt PDEs (Ben) - fixes and small improvements all over * tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel: (187 commits) drm/i915: Kill private_default_ctx off drm/i915: s/i915_hw_context/intel_context drm/i915: Split the ringbuffers from the rings (3/3) drm/i915: Split the ringbuffers from the rings (2/3) drm/i915: Split the ringbuffers from the rings (1/3) drm/i915: s/intel_ring_buffer/intel_engine_cs drm/i915: disable GT power saving early during system suspend drm/i915: fix possible RPM ref leaking during RPS disabling drm/i915: remove user GTT mappings early during runtime suspend drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk drm/i915: Fix gen2 and hsw+ scanline counter drm/i915: Draw a picture about video timings drm/i915: Improve gen3/4 frame counter drm/i915: Add a small adjustment to the pixel counter on interlaced modes drm/i915: Hold CRTC lock whilst freezing the planes drm/i915: Only discard backing storage on releasing the last ref drm/i915: Wait for pending page flips before enabling/disabling the primary plane drm/i915: grab the audio power domain when enabling audio on HSW+ drm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off drm/i915: move bsd dispatch index somewhere better ...
This commit is contained in:
Dave Airlie
@@ -3368,6 +3368,10 @@ void (*disable_vblank) (struct drm_device *dev, int crtc);</synopsis>
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with a call to <function>drm_vblank_cleanup</function> in the driver
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<methodname>unload</methodname> operation handler.
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</para>
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<sect2>
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<title>Vertical Blanking and Interrupt Handling Functions Reference</title>
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!Edrivers/gpu/drm/drm_irq.c
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</sect2>
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</sect1>
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<!-- Internals: open/close, file operations and ioctls -->
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@@ -3710,17 +3714,16 @@ int num_ioctls;</synopsis>
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<term>DRM_IOCTL_MODESET_CTL</term>
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<listitem>
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<para>
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This should be called by application level drivers before and
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after mode setting, since on many devices the vertical blank
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counter is reset at that time. Internally, the DRM snapshots
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the last vblank count when the ioctl is called with the
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_DRM_PRE_MODESET command, so that the counter won't go backwards
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(which is dealt with when _DRM_POST_MODESET is used).
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This was only used for user-mode-settind drivers around
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modesetting changes to allow the kernel to update the vblank
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interrupt after mode setting, since on many devices the vertical
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blank counter is reset to 0 at some point during modeset. Modern
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drivers should not call this any more since with kernel mode
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setting it is a no-op.
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</para>
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</listitem>
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</varlistentry>
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</variablelist>
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<!--!Edrivers/char/drm/drm_irq.c-->
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</para>
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</sect1>
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@@ -3783,6 +3786,96 @@ int num_ioctls;</synopsis>
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probing, so those sections fully apply.
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</para>
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</sect2>
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<sect2>
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<title>DPIO</title>
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!Pdrivers/gpu/drm/i915/i915_reg.h DPIO
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<table id="dpiox2">
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<title>Dual channel PHY (VLV/CHV)</title>
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<tgroup cols="8">
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<colspec colname="c0" />
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<colspec colname="c1" />
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<colspec colname="c2" />
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<colspec colname="c3" />
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<colspec colname="c4" />
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<colspec colname="c5" />
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<colspec colname="c6" />
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<colspec colname="c7" />
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<spanspec spanname="ch0" namest="c0" nameend="c3" />
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<spanspec spanname="ch1" namest="c4" nameend="c7" />
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<spanspec spanname="ch0pcs01" namest="c0" nameend="c1" />
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<spanspec spanname="ch0pcs23" namest="c2" nameend="c3" />
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<spanspec spanname="ch1pcs01" namest="c4" nameend="c5" />
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<spanspec spanname="ch1pcs23" namest="c6" nameend="c7" />
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<thead>
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<row>
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<entry spanname="ch0">CH0</entry>
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<entry spanname="ch1">CH1</entry>
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</row>
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</thead>
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<tbody valign="top" align="center">
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<row>
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<entry spanname="ch0">CMN/PLL/REF</entry>
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<entry spanname="ch1">CMN/PLL/REF</entry>
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</row>
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<row>
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<entry spanname="ch0pcs01">PCS01</entry>
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<entry spanname="ch0pcs23">PCS23</entry>
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<entry spanname="ch1pcs01">PCS01</entry>
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<entry spanname="ch1pcs23">PCS23</entry>
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</row>
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<row>
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<entry>TX0</entry>
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<entry>TX1</entry>
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<entry>TX2</entry>
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<entry>TX3</entry>
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<entry>TX0</entry>
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<entry>TX1</entry>
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<entry>TX2</entry>
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<entry>TX3</entry>
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</row>
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<row>
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<entry spanname="ch0">DDI0</entry>
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<entry spanname="ch1">DDI1</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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<table id="dpiox1">
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<title>Single channel PHY (CHV)</title>
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<tgroup cols="4">
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<colspec colname="c0" />
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<colspec colname="c1" />
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<colspec colname="c2" />
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<colspec colname="c3" />
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<spanspec spanname="ch0" namest="c0" nameend="c3" />
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<spanspec spanname="ch0pcs01" namest="c0" nameend="c1" />
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<spanspec spanname="ch0pcs23" namest="c2" nameend="c3" />
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<thead>
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<row>
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<entry spanname="ch0">CH0</entry>
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</row>
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</thead>
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<tbody valign="top" align="center">
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<row>
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<entry spanname="ch0">CMN/PLL/REF</entry>
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</row>
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<row>
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<entry spanname="ch0pcs01">PCS01</entry>
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<entry spanname="ch0pcs23">PCS23</entry>
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</row>
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<row>
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<entry>TX0</entry>
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<entry>TX1</entry>
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<entry>TX2</entry>
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<entry>TX3</entry>
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</row>
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<row>
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<entry spanname="ch0">DDI2</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</sect2>
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</sect1>
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<sect1>
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