ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
Adds clock setting entries for EXYNOS4212 and EXYNOS4412 platforms. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> [fixed compilation warning which is reported by Arnd Bergmann] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
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struct clk *xusbxti_clk;
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u32 phyclk;
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
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xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
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if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
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switch (clk_get_rate(xusbxti_clk)) {
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case 12 * MHZ:
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phyclk |= CLKSEL_12M;
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break;
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case 24 * MHZ:
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phyclk |= CLKSEL_24M;
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break;
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default:
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case 48 * MHZ:
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/* default reference clock */
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break;
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if (soc_is_exynos4210()) {
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
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switch (clk_get_rate(xusbxti_clk)) {
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case 12 * MHZ:
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phyclk |= EXYNOS4210_CLKSEL_12M;
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break;
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case 48 * MHZ:
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phyclk |= EXYNOS4210_CLKSEL_48M;
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break;
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default:
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case 24 * MHZ:
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phyclk |= EXYNOS4210_CLKSEL_24M;
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break;
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
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/* set clock frequency for PLL */
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phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
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switch (clk_get_rate(xusbxti_clk)) {
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case 9600 * KHZ:
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phyclk |= EXYNOS4X12_CLKSEL_9600K;
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break;
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case 10 * MHZ:
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phyclk |= EXYNOS4X12_CLKSEL_10M;
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break;
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case 12 * MHZ:
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phyclk |= EXYNOS4X12_CLKSEL_12M;
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break;
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case 19200 * KHZ:
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phyclk |= EXYNOS4X12_CLKSEL_19200K;
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break;
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case 20 * MHZ:
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phyclk |= EXYNOS4X12_CLKSEL_20M;
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break;
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default:
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case 24 * MHZ:
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/* default reference clock */
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phyclk |= EXYNOS4X12_CLKSEL_24M;
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break;
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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}
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clk_put(xusbxti_clk);
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}
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writel(phyclk, EXYNOS4_PHYCLK);
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}
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static int exynos4210_usb_phy0_init(struct platform_device *pdev)
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