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PCI: cadence: Allow pci_host_bridge to have custom pci_ops

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Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.

Link: https://lore.kernel.org/r/20200722110317.4744-7-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This commit is contained in:
Kishon Vijay Abraham I
2020-07-22 16:33:08 +05:30
committed by Lorenzo Pieralisi
parent 40d957e6f9
commit c4c10c0125
1 changed files with 2 additions and 1 deletions
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3
drivers/pci/controller/cadence/pcie-cadence-host.c
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@@ -506,7 +506,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
list_splice_init(&resources, &bridge->windows);
bridge->dev.parent = dev;
bridge->busnr = pcie->bus;
bridge->ops = &cdns_pcie_host_ops;
if (!bridge->ops)
bridge->ops = &cdns_pcie_host_ops;
bridge->map_irq = of_irq_parse_and_map_pci;
bridge->swizzle_irq = pci_common_swizzle;