[SPARC64]: Deal with PTE layout differences in SUN4V.
Yes, you heard it right, they changed the PTE layout for SUN4V. Ho hum... This is the simple and inefficient way to support this. It'll get optimized, don't worry. Signed-off-by: David S. Miller <davem@davemloft.net>
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@@ -23,8 +23,6 @@
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* disable preemption during the clear.
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*/
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#define TTE_BITS_TOP (_PAGE_VALID | _PAGE_SZBITS)
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#define TTE_BITS_BOTTOM (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W)
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#define DCACHE_SIZE (PAGE_SIZE * 2)
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#if (PAGE_SHIFT == 13) || (PAGE_SHIFT == 19)
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@@ -52,13 +50,12 @@ copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
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sethi %hi(PAGE_SIZE), %o3
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sllx %g2, 32, %g2
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sethi %uhi(TTE_BITS_TOP), %g3
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sethi %hi(PAGE_KERNEL_LOCKED), %g3
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sllx %g3, 32, %g3
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ldx [%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3
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sub %o0, %g2, %g1 ! dest paddr
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sub %o1, %g2, %g2 ! src paddr
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or %g3, TTE_BITS_BOTTOM, %g3
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and %o2, %o3, %o0 ! vaddr D-cache alias bit
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or %g1, %g3, %g1 ! dest TTE data
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